An efficiency of 8.6% on Cu2ZnSnS4 (CZTS) submodule is achieved by revising absorber formation and optimizing buffer layer thickness with the improved absorber. The CZTS submodule is fabricated by following process. Mo back electrode and metal precursor are deposited by vacuum-based processes. The CZTS absorber layer is formed through high-temperature annealing with sulfur containing gas. CdS buffer layer and ZnO window layer are then deposited by chemical bath deposition and metal-organic chemical vapor deposition, respectively. In this paper, we focus on the CZTS absorber uniformity and its thickness. Buffer thickness is also optimized. At first, performance of submodules with void-rich absorber and void-free absorber is investigated. Then, the impact of absorber thickness is investigated. We observe that thinner absorbers contribute to higher open circuit voltage whereas void-free absorbers contribute to higher fill factor. Over 8% submodule efficiency is achieved with void-free ultra-thin CZTS absorber layer with only 600 nm in thickness. Electron beam induced current (EBIC) mapping is performed to map out the distribution of current collection. The EBIC result clearly shows that the void-free and ultra-thin absorber has uniform and wide EBIC distribution. In addition, re-optimization of buffer layer thickness for the void-free and ultra-thin absorber further boosts the performance. We find that thinner CdS which lead to less absorption loss at short wavelength region works well with the void-free ultra-thin absorber. Further optimization will contribute to the development of lower cost and higher productivity CZTS fabrication process.
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