"ŠÖŒû‹M”V,•ôŽRˆŸŠóŽq,—é–Ø�r�G,ˆÉ“¡�_”V,“V�ì�C•½,�ÎŒ´�¸,‰v ˆê�Æ","90nmƒvƒ�ƒZƒX‚É‚æ‚é20Gb/sNear-Rail-to-Rail ƒ�ƒWƒbƒN“®�ì1:4 DEMUX","“dŽq�î•ñ’Ê�MŠw‰ï ƒVƒŠƒRƒ“ƒAƒiƒ�ƒORFŒ¤‹†‰ï","“dŽq�î•ñ’Ê�MŠw‰ï ƒVƒŠƒRƒ“ƒAƒiƒ�ƒORFŒ¤‹†‰ï","“dŽq�î•ñ’Ê�MŠw‰ï",,,"p. 6",2009,July
"A. Mineyama,T. Suzuki,H. Ito,S. Amakawa,N. Ishihara,K. Masu","A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process","2009 IEEE MTT-S International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects (IMWS2009-R9)","2009 IEEE MTT-S International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects (IMWS2009-R9)",,,,"pp. 119-122",2009,Feb.
"Akiko Mineyama,Hiroyuki Ito,Takahiro Ishii,Kenichi Okada,Kazuya Masu","LVDS-type On-Chip Transmision Line Interconnect with Passive Equalizers in 90 nm CMOS Process","IEEE/ACM Asia and South Pacific Design Automation Conference (Design Contest)","IEEE/ACM Asia and South Pacific Design Automation Conference (Design Contest)",,,,,2008,Jan.
"•ôŽRˆŸŠóŽq,�Έ䗲�G,–Ø‘ºŽÀ�l,ˆÉ“¡�_”V,‰ª“cŒ’ˆê,”©ŽR‰pŽ÷,‘ŠàV‘ì–ç,ˆÉ“¡’B–ç,ŽR“à—ÇŽO,‰v ˆê�Æ","WLCSP‹Z�p‚ð—˜—p‚µ‚½ƒIƒ“ƒ`ƒbƒv“`‘—�ü˜H”z�ü‚ÌŒŸ“¢","“dŽq�î•ñ’Ê�MŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ï",,,,"No. C-12-45","pp. 100",2007,Sept.
"•ôŽRˆŸŠóŽq,�Έ䗲�G,–Ø‘ºŽÀ�l,ˆÉ“¡�_”V,‰ª“cŒ’ˆê,”©ŽR‰pŽ÷,‘ŠàV‘ì–ç,ˆÉ“¡’B–ç,ŽR“à—ÇŽO,‰v ˆê�Æ","WLCSP‹Z�p‚ð—p‚¢‚½’á�Á”ï“d—̓Iƒ“ƒ`ƒbƒv“`‘—�ü˜H”z�ü‚Ì�ÝŒv","VDECƒfƒUƒCƒi�[ƒtƒH�[ƒ‰ƒ€",,,,,,2007,Sept.