"Koh Yamanaga,Shuhei Amakawa,Kazuya Masu,Takashi Sato","A Universal Equivalent Circuit Model for Ceramic Capacitors","IEICE Transactions on Fundamentals of Electronics","IEICE Transactions on Fundamentals of Electronics","IEICE Transactions on Fundamentals of Electronics","Vol. E93-C","No. 3","pp. 347-354",2010,Mar.
"Shiho Hagiwara,Koh Yamanaga,Ryo Takahashi,Kazuya Masu,Takashi Sato","Linear Time Calculation of State-Dependent Power Distribution Network Capacitance.","International Symposium on Quality Electronic Design (ISQED)","International Symposium on Quality Electronic Design (ISQED)","International Symposium on Quality Electronic Design (ISQED)",,,"pp. 75-80",2010,Mar.
"K. Yamanaga,S. Amakawa,T. Sato,K. Masu","Two-Dimentional Moment Method for Analyzing Current Distribution of a Ceramic Capacitor","2009 International Symposium on Electromagnetic Comptibility, Kyoto","2009 International Symposium on Electromagnetic Comptibility","IEICE",,,"pp. 575-578",2009,July
"S. Amakawa,K. Yamanaga,H. Ito,T. Sato,N. Ishihara,K. Masu","S-parameter-based modal decomposition of multiconductor transmission lines and its application to de-embedding","International Conference on Microelectronic Test Structures (ICMTS)","International Conference on Microelectronic Test Structures (ICMTS)",,,,"pp. 177-180",2009,Apr.
"Koh Yamanaga,Takashi Sato,Kazuya Masu","2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept",,"IEICE Transactions on Fundamentals of Electronics","IEICE Transactions on Fundamentals of Electronics","Vol. E92-A","No. 4","pp. 976-982",2009,Apr.
"萩原 汐,高橋 亮,山長 功,佐藤 高史,益 一哉","状態依存性を考慮した論理回路の電源間容量モデルの検討","2009 年 電子情報通信学会総合大会","2009 年 電子情報通信学会総合大会","電子情報通信学会",,,"  C-12-30",2009,Mar.
"山長 功,高橋 亮,萩原 汐,佐藤 高史,益 一哉","状態依存性解析のための電源間容量のテーブルルックアップ計算","2009 年 電子情報通信学会総合大会","2009 年 電子情報通信学会総合大会","電子情報通信学会",,,"  C-12-31",2009,Mar.
"Takashi Sato,Koh Yamanaga,Kazuya Masu","Non-invasive direct probing for on-chip voltage measurement","International SoC design conference (ISOCC)","International SoC design conference (ISOCC)",,,,"pp. 350-353",2008,Nov.
"Koh Yamanaga,Takashi Sato,Kazuya Masu","Accurate parasitic inductance determination of a ceramic capacitor through 2-port measurements","17th Conference on Electrical Performance of Electronic Packaging (EPEP)","17th Conference on Electrical Performance of Electronic Packaging (EPEP)",,,,"pp. 119-122",2008,Oct.
"高橋亮,山長功,佐藤高史,益一哉","CMOS論理回路における電源網容量の入力状態依存性についての検討","電子情報通信学会ソサエティ大会","電子情報通信学会ソサエティ大会",,,"  C-12-42","pp. 111",2008,Sept.
"Koh Yamanaga,Takashi Sato,Masu Kazuya","On-chip differential and common mode voltage measurement using off-chip referenced twin probing","12th SPI","12th SPI",,,,"pp. 331-336",2008,May
"Koh Yamanaga,Takashi Sato,Masu Kazuya","Substrate-geometry aware 2-port modeling for surface-mount passive components","Asia-Pacific EMC Week 2008","Asia-Pacific EMC Week 2008",,,,"pp. 246-249",2008,May
"山長功,佐藤高史,益 一哉","基板実装状態を考慮可能な表面実装型受動部品の2ポートモデリング手法","第21回 回路とシステム軽井沢ワークショップ","第21回 回路とシステム軽井沢ワークショップ",,,,"pp. 331-336",2008,Apr.
"山長功,佐藤高史,益 一哉","測定系の侵襲性を定量化可能なオンチップ電源電圧変動の直接測定手法","電子情報通信学会総合大会","電子情報通信学会総合大会",,,,"pp. C-12-37",2008,Mar.