"Masashi Imai,Thiem Van Chu,Kenji Kise,Tomohiro Yoneda","The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs,","IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)",,,,,,2016,Sept.
"Tomohiro Yoneda,Masashi Imai,Hiroshi Saito,Kenji Kise","Dependable real-Time Task Execution Scheme for a Many-Core Platform","International Symposium on Defect and Fault Tolerance in VLSI and nanotechnologh Systems (DFT2015)",,,,,,2015,Oct.
"Bin Zhou,Tomohiro Yoneda,Chris Myers","Framework of Timed Trace Theoretic Verification Revisited",,"Proc. of 10th Asian Test Symposium",,,,"pp. 437-442",2001,
"Eric Mercer,Chris Myers,Tomohiro Yoneda","Improved poset timing analysis in timed Petri nets",,"Proc. of The 10th Workshop on Synthesis And System Integration of Mixed Technologies",,,,"pp. 127-134",2001,
"Tomohiro Yoneda,Eric Mercer,Chris Myers","Modular Synthesis of Timed Circuits using Partial Order Reduction",,"Proc. of The 10th Workshop on Synthesis And System Integration of Mixed Technologies",,,,"pp. 151-158",2001,
"米田友洋","有限幅遅延モデルに基づく非同期式回路検証方式とその効率化",,"システム/制御/情報",,"Vol. 45","No. 8","pp. 461-469",2001,
"Bin Zhou,Tomohiro Yoneda,Holger Schlingloff","Conformance and Mirroring for Timed Asynchronous Circuits",,"Proc. of ASP-DAC'01",,,,"pp. 341-346",2001,
"森広芳文,米田友洋","シミュレーションを利用した形式的検証システム",,"電子情報通信学会和文論文誌",,"Vol. J84-D-I","No. 4","pp. 367-377",2001,
"Tomoya Kitai,Tomohiro Yoneda","Partial order reduction in verification of wheel structured parameterized circuits",,"Proc. of 2001 Pacific Rim International Symposium on Dependable Computing",,,,,2001,
"北井智也,米田友洋","星状抽象ペトリネットの解析に関する研究",,"電子情報通信学会技術研究報告",,"Vol. FTS-2000","No. 59","pp. 149-154",2000,
"小黒裕介,岡埜 靖,米田友洋","データパスを含む非同期式回路の検証について",,"電子情報通信学会技術研究報告",,"Vol. FTS-2000","No. 9","pp. 65-72",2000,
"Yoshifumi Morihiro,Tomohiro Yoneda","Verifying Stacks and Queues Using Symbolic Simulation Techniques",,"Proc. of 2000 International Workshop on RTL ATPG & DFT",,,,"pp. 119-128",2000,
"米田友洋","ペトリネット理論の非同期式回路検証への応用",,"第13回回路とシステムワークショップ論文集",,,,"pp. 421-426",2000,
"Tomohiro Yoneda","VINAS-P: A tool for trace theoretic verification of timed asynchronous circuits",,"Proc. of Computer Aided Verification, LNCS 1855",,,,"pp. 572-575",2000,
"Mart Saarepera,Tomohiro Yoneda","Implementation of Quasi Delay-Insensitive Boolean Function Blocks",,"Journal of IEICE",,"Vol. E83-D","No. 10","pp. 1879-1889",2000,
"Yoshifumi Morihiro,Tomohiro Yoneda","Formal Verification of Data-Path Circuits based on Symbolic Simulation",,"Proc. of 9th Asian Test Symposium",,,,"pp. 329-336",2000,
"TOMOHIRO YONEDA","Verification of Abstracted Instruction Cache of TITAC2",,"Proc. of X IFIP International Conference on Very Large Scale Integration",,,,"pp. 373-387",1999,
"Tomohiro Yoneda,Bin Zhou,Bernd--Holger Schlingloff","Verification of bounded delay asynchronous circuits with timed traces",,"Proc. of 7th International Conference on Algebraic Methodology and Software Technology (AMAST'98)",,,,"pp. 59-73",1999,
"Atsushi Yamazaki,Hiroshi Ryu,Tomohiro Yoneda","Verification of Scalable-Delay-Insensitive asynchronous circuits",,"Journal of IEICE, Letter",,"Vol. E82-D","No. 3","pp. 701-703",1999,
"Minoru TOMISAKA,Tomohiro Yoneda","Partial Order Reduction in Symbolic State Space Traversal Using ZBDDs",,"Journal of IEICE, Letter",,"Vol. E82-D","No. 3","pp. 704-711",1999,
"Tomohiro Yoneda,Hiroshi Ryu","Timed Trace Theoretic Verification Using Partial Order Reduction",,"Proc. of Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)",,,,"pp. 108-121",1999,
"Mart Saarepera,Tomohiro Yoneda","A Self-Timed Implementation of Boolean Functions",,"Proc. of Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)",,,,"pp. 243-250",1999,
"増倉 孝一,富坂 稔,米田 友洋","ZBDDに基づく非同期式回路の検証方式",,"電子情報通信学会和文論文誌",,"Vol. J82-D-I","No. 6","pp. 760-771",1999,
"戸島弘詩,米田 友洋","対称性及び抽象化を利用した検証方式の効率化",,"電子情報通信学会和文論文誌",,"Vol. J82-D-I","No. 7","pp. 799-811",1999,
"周 斌,米田 友洋","有限遅延幅モデルにおける非同期式回路の検証について",,"電子情報通信学会和文論文誌",,"Vol. J82-D-I","No. 7","pp. 819-833",1999,
"TOMOHIRO YONEDA","Verification of Abstracted Instruction Cache of TITAC2",,"Proc. of X IFIP International Conference on Very Large Scale Integration",,,,"pp. 373-387",1999,
"Tomohiro Yoneda,Bin Zhou,Bernd-Holger Schlingloff","Verification of bounded delay asynchronous circuits with timed traces",,"Proc. of 7th International Conference on Algebraic Methodology and Software Technology (AMAST'98)",,,,"pp. 59-73",1999,
"Tomohiro Yoneda,Hiroshi Ryu","Timed Trace Theoretic Verification Using Partial Order Reduction",,"Proc. of Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)",,,,"pp. 108-121",1999,
"米田友洋","非同期式回路の検証におけるlivenessクラスに関する考察",,"電子情報通信学会和文論文誌",,"Vol. J81-D-I","No. 4","pp. 405-416",1998,
"TOMOHIRO YONEDA","CTL Model Checking of Time Petri Nets Using Geometric Regions",,"Journal of IEICE",,"Vol. E81-D","No. 3","pp. 297-396",1998,
"TOMOHIRO YONEDA","Verification of parameterized asynchronous circuits : A case study ;",,"International Conference on Application of Concurrency to System Design(CSD'98)",,,,"pp. 64-74",1998,
"米田友洋","プロセス代数に基づく非同期式論理回路の設計検証",,"電子情報通信学会論文誌",,"Vol. J80-DI","No. 3","pp. 207-217",1997,
"米田友洋","n安全タイムペトリネットの発火規則について",,"電子情報通信学会研究速報",,"Vol. J80-A","No. 12","pp. 2177-2183",1997,
"TOMOHIRO YONEDA","Efficient Verification of Parallel Real-Time Systems ; Formal Methods in System Design",,"Kluwer Academic Publishers",,"Vol. 11","No. 2","pp. 187-215",1997,
"TOMOHIRO YONEDA","BDDs vs. Zero-Suppressed BDDs : for CTL symbolic model checking of Petri nets",,"Lecture Note in Computer Science 1166",,,,"pp. 435-449",1996,
"米田友洋","タイムペトリネットのCTL記号モデル検査",,"電子情報通信学会論文誌",,"Vol. J79-A","No. 6","pp. 1194-1203",1996,
"TOMOHIRO YONEDA","Using partial orders for trace theoretic verification of asynchronous circuits",,"Pro.of Second International Symposium on Advanced Research in Asynchronous Circuits and Systems",,,,"pp. 152-163",1996,
"TOMOHIRO YONEDA","Discete analysis of time Petri nets",,"Proc.of the 1995 Pacific Rim International Symposium on Fault Tolerant Systems",,,,"pp. 224-229",1995,
"TOMOHIRO YONEDA","Verification of schedulability of real-time systems with extended time Petri nets",,"Proc.of the Third Workshop on Parallel and Distributed Real-Time Systems",,,,"pp. 185-192",1995,
"TOMOHIRO YONEDA","Improving a fault-tolerant clock synchronization algorithm by overcorrection",,"Computer Systems Science & Engineering",,"Vol. 9","No. 1","pp. 54-64",1994,
"TOMOHIRO YONEDA","Efficient verification of parallel real-time systems (共著)",,"Lecture Note in Computer Science",,"Vol. 697",,"pp. 321-332",1993,
"宮崎純,米田友洋,当麻喜弘","拡張時間順序機械に基づく自動タイミング検証方式の並列化",,"情報処理学会研究報告システムLSI設計技術",,"Vol. 92","No. 83","pp. 87-94",1992,Oct.
"TOMOHIRO YONEDA","Acceleration of timing verification method based on time Petri nets",,"Systems and Computers in Japan",,"Vol. 22","No. 12","pp. 37-52",1991,
"TOMOHIRO YONEDA","A Fast Timing Verification Method Based on the Independence of Units",,"Proceedings of 19th International Symposium on Fault-Tolerant Computing",,,,"pp. 134-141",1989,
"TOMOHIRO YONEDA","The Container Concept for Relaying Packets in Fault-Tolerant Computer Networks",,"Proceedings of 16th International Symposium on Fault-Tolerant Computing",,,,"pp. 190-195",1986,
"TOMOHIRO YONEDA","Implementation of Interrupt Handler for Loosely-Synchronized TMR Systems",,"Proceedings of 15th International Symposium on Fault-Tolerant Computing",,,,"pp. 246-251",1985,
"米田友洋","マイクロコンピュータ複合体の耐故障設計とその応用に関する研究",,,,,,,1985,