"K. Yamanaga,S. Amakawa,T. Sato,K. Masu","Two-Dimentional Moment Method for Analyzing Current Distribution of a Ceramic Capacitor","2009 International Symposium on Electromagnetic Comptibility, Kyoto","2009 International Symposium on Electromagnetic Comptibility","IEICE",,,"pp. 575-578",2009,July
"Kazuya Masu,Noboru Ishihara,Noriaki Nakayama,Takashi Sato,Shuhei  Amakawa","Physical design challenges to nano-CMOS circuits","IEICE Electronics Express (ELEX)","IEICE Electronics Express (ELEX)","IEICE Electronics Express (ELEX)","Vol. 6","No. 11","pp. 703-720",2009,June
"伊達貴徳,萩原 汐,上薗 巧,佐藤高史,益 一哉","SRAM回路の構造的対称性を考慮した2段階学習型重点的サンプリング","VLSI設計技術研究会 システム設計及び一般","VLSI設計技術研究会 システム設計及び一般，信学技報","VLSI設計技術研究会 システム設計及び一般","vol. 109","no. 34","pp. 37-42",2009,May
"S. Amakawa,K. Yamanaga,H. Ito,T. Sato,N. Ishihara,K. Masu","S-parameter-based modal decomposition of multiconductor transmission lines and its application to de-embedding","International Conference on Microelectronic Test Structures (ICMTS)","International Conference on Microelectronic Test Structures (ICMTS)",,,,"pp. 177-180",2009,Apr.
"Shiho Hagiwara,Takashi Sato,Kazuya Masu","Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits",,"IEICE Transactions on Fundamentals of Electronics","IEICE Transactions on Fundamentals of Electronics","Vol. E92-A","No. 4","pp. 1031-1038",2009,Apr.
"Koh Yamanaga,Takashi Sato,Kazuya Masu","2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept",,"IEICE Transactions on Fundamentals of Electronics","IEICE Transactions on Fundamentals of Electronics","Vol. E92-A","No. 4","pp. 976-982",2009,Apr.
"Takumi Uezono,Takashi Sato,Kazuya Masu","One-Shot Voltage-Measurement Circuit Utilizing Process Variation",,"IEICE Transactions on Fundamentals of Electronics","IEICE Transactions on Fundamentals of Electronics","Vol. E92-A","No. 4","pp. 1024-1030",2009,Apr.
"上薗 巧,高橋 知之,植山 寛之,新谷 道広,佐藤 高史,益 一哉","適応型テストにおけるクリティカルパスのクラスタリング手法","2009 年 電子情報通信学会総合大会","2009 年 電子情報通信学会総合大会","電子情報通信学会",,"  D-10-17","p. 160",2009,Mar.
"新谷 道広,高橋 知之,植山 寛之,上薗 巧,佐藤 高史,畠山 一実,相京 隆,益 一哉","統計的タイミング情報に基づく適応型テスト",,"2009 年 電子情報通信学会総合大会",,,,"  D-10-16",2009,Mar.
"山長 功,高橋 亮,萩原 汐,佐藤 高史,益 一哉","状態依存性解析のための電源間容量のテーブルルックアップ計算","2009 年 電子情報通信学会総合大会","2009 年 電子情報通信学会総合大会","電子情報通信学会",,,"  C-12-31",2009,Mar.
"萩原 汐,高橋 亮,山長 功,佐藤 高史,益 一哉","状態依存性を考慮した論理回路の電源間容量モデルの検討","2009 年 電子情報通信学会総合大会","2009 年 電子情報通信学会総合大会","電子情報通信学会",,,"  C-12-30",2009,Mar.
"山田健太,庄 俊之,國清辰也,庄 俊之,益 一哉,中山範明,佐藤高史,天川修平,吉村尚郎,伊藤 優,熊代成孝","STIストレスによるMOSFET特性変動のコンパクトモデル","2009年（平成21年）第56回応用物理学関係連合講演会","2009年（平成21年）第56回応用物理学関係連合講演会",,,,"  31p-G-3",2009,Mar.
"Takashi Sato,Koh Yamanaga,Kazuya Masu","Non-invasive direct probing for on-chip voltage measurement","International SoC design conference (ISOCC)","International SoC design conference (ISOCC)",,,,"pp. 350-353",2008,Nov.
"Takashi Sato,Hiroyuki Ueyama,Noriaki Nakayama,Kazuya Masu","A MOS transistor array with pico-ampere order precision for accurate characterization of leakage current variation","IEEE Asian solid-state circuit conference (ASSCC)","IEEE Asian solid-state circuit conference (ASSCC)","IEEE Asian solid-state circuit conference (ASSCC)",,,"pp. 389-392",2008,Nov.
"Noriaki Nakayama,Takashi Sato,Hiroyuki Ueyama,Kazuya Masu","An efficient extraction of random and systematic gate-length variation through poly-Si resistor measurement","Workshop on test structure design for variability characterization","Workshop on test structure design for variability characterization",,,,,2008,Nov.
"Koh Yamanaga,Takashi Sato,Kazuya Masu","Accurate parasitic inductance determination of a ceramic capacitor through 2-port measurements","17th Conference on Electrical Performance of Electronic Packaging (EPEP)","17th Conference on Electrical Performance of Electronic Packaging (EPEP)",,,,"pp. 119-122",2008,Oct.
"高橋亮,山長功,佐藤高史,益一哉","CMOS論理回路における電源網容量の入力状態依存性についての検討","電子情報通信学会ソサエティ大会","電子情報通信学会ソサエティ大会",,,"  C-12-42","pp. 111",2008,Sept.
"植山寛之,佐藤高史,中山範明,益 一哉","抵抗測定法によるトランジスタアレイ回路の測定時間短縮化","電子情報通信学会ソサイエティ大会","電子情報通信学会ソサイエティ大会",,,"  C-12-41","pp. 110",2008,Sept.
"伊達貴徳,萩原 汐,佐藤高史,中山範明,益 一哉","回路特性ばらつき解析に対する重点的サンプリングの適用検討","電子情報通信学会ソサイエティ大会","電子情報通信学会ソサイエティ大会",,,"  A-1-27","pp. 27",2008,Sept.
"高橋知之,植山寛之,萩原 汐,佐藤高史,益 一哉","論理セル遅延の電圧・プロセスばらつき感度の検討","電子情報通信学会ソサイエティ大会","電子情報通信学会ソサイエティ大会",,,"  A-3-2","pp. 52",2008,Sept.
"Kenta Yamada,Takashi Sato,Noriaki Nakayama,Shuhei Amakawa,Kazuya Masu","Layout-aware compact model of MOSFET characteristics variations induced by STI stress",,"IEICE Transactions on Electronics",,"Vol. E91-C","No. 7","pp. 1142-1150",2008,July
"Masanori Imai,Takashi Sato,Noriaki Nakayama,Kazuya Masu","Non-Parametric StatisticalStatic TimingAnalysis: An SSTA Framework for Arbitrary Distribution","45th Design Automation Conference (DAC)","45th Design Automation Conference (DAC)",,,,"pp. 698-701",2008,June
"Koh Yamanaga,Takashi Sato,Masu Kazuya","On-chip differential and common mode voltage measurement using off-chip referenced twin probing","12th SPI","12th SPI",,,,"pp. 331-336",2008,May
"Koh Yamanaga,Takashi Sato,Masu Kazuya","Substrate-geometry aware 2-port modeling for surface-mount passive components","Asia-Pacific EMC Week 2008","Asia-Pacific EMC Week 2008",,,,"pp. 246-249",2008,May
"萩原汐,佐藤高史,益 一哉","電源遮断回路におけるパス遅延時間ばらつきの計算","第21回 回路とシステム軽井沢ワークショップ","第21回 回路とシステム軽井沢ワークショップ",,,,"pp. 427-432",2008,Apr.
"Shiho Hagiwara,Takumi Uezono,Takashi Sato,Kazuya Masu","Application of Correlation-based Regression Analysis for Improvement of Power Distribution Network",,"IEICE Transactions on Fundamentals of Electronics",,"Vol. E91-A","No. 5","pp. 951-956",2008,Apr.
"Masanori Imai,Takashi Sato,Noriaki Nakayama,Kazuya Masu","An evaluation method for the number of Monte Carlo STA trials",,"IEICE Transactions on Fundamentals",,"Vol. E91-A","No. 4","pp. 957-964",2008,Apr.
"上薗巧,佐藤高史,益 一哉","プロセスばらつきの積極的活用による非繰返し電圧波形の測定","第21回 回路とシステム軽井沢ワークショップ","第21回 回路とシステム軽井沢ワークショップ",,,,"pp. 439-444",2008,Apr.
"山長功,佐藤高史,益 一哉","基板実装状態を考慮可能な表面実装型受動部品の2ポートモデリング手法","第21回 回路とシステム軽井沢ワークショップ","第21回 回路とシステム軽井沢ワークショップ",,,,"pp. 331-336",2008,Apr.
"植山寛之,佐藤高史,中山範明,益 一哉","リーク電流測定用トランジスタアレイ回路の測定","電子情報通信学会 総合大会","電子情報通信学会 総合大会",,,,"pp. A-3-14",2008,Mar.
"益一哉,萩原 汐,佐藤 高史","電源遮断回路におけるインバータ列遅延時間ばらつきの計算","電子情報通信学会 総合大会","電子情報通信学会 総合大会",,,,"pp. A-3-7,",2008,Mar.
"植山寛之,佐藤高史,中山範明,益 一哉","リーク電流測定用トランジスタアレイ回路の測定","電子情報通信学会 総合大会","電子情報通信学会 総合大会",,,"  A-3-14","pp. 89",2008,Mar.
"山長功,佐藤高史,益 一哉","測定系の侵襲性を定量化可能なオンチップ電源電圧変動の直接測定手法","電子情報通信学会総合大会","電子情報通信学会総合大会",,,,"pp. C-12-37",2008,Mar.
"Takashi Sato,Hiroyuki Ueyama,Noriaki Nakayama,Kazuya Masu","Determination of optimal polynomial regression function to decompose on-die systematic and random variations","ACM/IEEE Asia South Pacific Design Automation Conference (ASPDAC)","ACM/IEEE Asia South Pacific Design Automation Conference (ASPDAC)",,,,"pp. 518-523",2008,Jan.
"萩原汐,佐藤高史,益一哉","パワーゲーティング技術における製造ばらつきの回路特性への影響","第131回 システムLSI設計技術研究発表会 (ICD/SIP/IE/SLDM合同研究会)",,,,,,2007,Oct.
"上薗巧,佐藤高史,益一哉","電源電圧降下の時間的・空間的広がり可視化回路","VDECデザイナーフォーラム",,,,,,2007,Sept.
"植山寛之,佐藤高史,中山範明,益 一哉","大域ばらつきの近似次数が回路遅延ばらつきに与える影響","電子情報通信学会ソサイエティ大会",,,,"No. A-1-8","pp. 8",2007,Sept.
"上薗巧,佐藤高史,益一哉","電源電圧降下の時間的・空間的広がり可視化手法","電子情報通信学会ソサイエティ大会",,,,"No. C-12-6",,2007,Sept.
"植山寛之,佐藤高史,中山範明,益 一哉","閾値電圧の大域ばらつきが回路遅延ばらつきに与える影響","STARCシンポジウム",,,,,,2007,Sept.
"Takashi Sato,Shiho Hagiwara,Takumi Uezono,Kazuya Masu","Weakness identification for effective repair of power distribution network","17th International workshop on power and timing modeling, optimization and simulation (PATMOS)",,,,,"pp. 222-231",2007,Sept.
"今井 正紀,佐藤 高史,中山 範明,益 一哉","ノンパラメトリック統計的タイミング解析 (SSTA) の実現手法の検討","DA シンポジウム",,,,,"pp. 121-126",2007,Aug.
"萩原汐,上薗巧,佐藤高史,益 一哉","相関係数にもとづく回帰分析の電源改善への適用","第20回 回路とシステム軽井沢ワークショップ",,,,,"pp. 45-50",2007,Apr.
"今井正紀,佐藤 高史,中山 範明,益 一哉","統計的パス遅延解析のためのMonte Carlo STA実行数評価の一手法","第20回 回路とシステム軽井沢ワークショップ",,,,,"pp. 703-708",2007,Apr.
"萩原 汐,上薗 巧,佐藤 高史,益 一哉","電源電圧降下の相関を用いる電源網の定量的評価","電子情報通信学会 総合大会",,,,"No. A-3-7",,2007,Mar.
"Takashi Sato,Takumi Uezono,Shiho Hagiwara,Kenichi Okada,Shuhei Amakawa,Noriaki Nakayama,Kazuya Masu","A MOS transistor-array for accurate measurement of subthreshold leakage variation","International Symposium on Quality Electronic Design (ISQED)",,,,,"pp. 21-26",2007,Mar.
"Shuhei Amakawa,Takumi Uezono,Takashi Sato,Kenichi Okada,Kazuya Masu","Adaptable wire-length distribution with tunable occupation probability","International Workshop on System Level Interconnect Prediction (SLIP)",,"ACM",,,"pp. 1-8",2007,Mar.
"Shiho Hagiwara,Takumi Uezono,Takashi Sato,Kazuya Masu","Improvement of power distribution network using correlation-based regression analysis","Great Lakes Symposium on VLSI (GLSVLSI)",,,,,"pp. 513-516",2007,Mar.
"天川 修平,上薗 巧,佐藤 高史,益 一哉","セル間接続方向限定性とセル配置粗密性を考慮した配線長分布","電子情報通信学会 総合大会",,,,"No. A-3-19","pp. 109",2007,Mar.
"Junki Seita,Hiroyuki Ito,Kenichi Okada,Takashi Sato,Kazuya Masu","A Multi-Drop Transmission-Line Interconnect in Si LSI","Asia and South Pacific Design Automation Conference",,,,,"pp. 118-119",2007,Jan.
"Jang-Gu Kim,Kenichi Okada,Tackya Yammouch,Takashi Sato,Kazuya Masu","An Left Handed Material on Si CMOS Chip with Wafer Level Package Process","IEEE Asia-Pacific Microwave Conference (APMC)",,,,,,2006,Dec.
"藤久 雄己,岡田 健一,佐藤 高史,中山 範明,益 一哉","MOSFETのサブスレッショルド電流ばらつき測定のための回路検討","電子情報通信学会 システムLSIワークショップ",,,,,"pp. 259-262",2006,Nov.
"Takashi Sato,Yu Matsumoto,Koji Hirakimoto,Michio Komoda,Junichi Mano","A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop","IEEE Custom Integrated Circuits Conference (CICC)",,,,,,2006,Sept.
"萩原汐,佐藤高史,益一哉","高精度デバイスばらつき測定のための電源構造の設計","電子情報通信学会 ソサエティ大会",,,,,"pp. A-3-21",2006,Sept.
"上薗巧,佐藤高史,益一哉","リングオシレータを用いる瞬時電圧降下測定手法の精度改善","電子情報通信学会 ソサエティ大会",,,,,"pp. A-3-23",2006,Sept.
"金 章九,山内拓弥,岡田健一,佐藤高史,益 一哉","Si CMOSチップにおける右手・左手系伝送線路の検討","電子情報通信学会 ソサエティ大会",,,,,"pp. C-12-36",2006,Sept.
"藤久 雄己,上薗 巧,萩原汐,岡田健一,佐藤高史,中山範明","MOSFETのリーク電流ばらつき測定のための回路検討","電子情報通信学会 ソサエティ大会",,,,,"pp. A-3-22",2006,Sept.
"清田 淳紀,伊藤 浩之,岡田 健一,佐藤 高史,益 一哉","伝送線路を用いたオンチップ高速信号伝送回路の研究","電子情報通信学会 ソサエティ大会",,,,,"pp. A-3-16",2006,Sept.
"萩原汐,佐藤高史,益一哉","デバイスばらつき測定用電源構造の改善","VDECデザイナーフォーラム",,,,,,2006,Sept.
"佐藤高史",,,,,,,,,