"木下昌紀,富岡洋一,高橋篤司","2層BGAパッケージのための詳細ビア配置手法の評価","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-117)",,"Vol. 109","No. 462","pp. 109-114",2010,Mar.
"高橋伸嘉,富岡洋一,小平行秀,高橋篤司","入力ベクトルと回路の内部状態を考慮したピーク電力高速見積もり手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-115)",,"Vol. 109","No. 462","pp. 97-102",2010,Mar.
"Yoichi Tomioka,Yoshiaki Kurata,Yukihide Kohira,Atsushi Takahashi","MILP-based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 12","pp. 2998-3006",2009,Dec.
"Yoichi Tomioka,Atsushi Takahashi","Top Layer Plating Lead Maximization for BGA Packages",,"Proc. the 2009 IEICE Society Conference (A-3-10)",,"Vol. A",,"p. 59",2009,Sept.
"木下昌紀,富岡洋一,高橋篤司","2層BGAパッケージにおける配線混雑度低減のための詳細ビア配置手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-30)",,"Vol. 109","No. 201","pp. 7-12",2009,Sept.
"高橋伸嘉,富岡洋一,小平行秀,高橋篤司","入力ベクトルの適切な選択によるピーク電力高速見積り手法",,"DAシンポジウム2009論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2009","No. 7","pp. 13-18",2009,Aug.
"Yoichi Tomioka,Atsushi Takahashi","Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 6","pp. 1433-1441",2009,June
"井上雅文,富岡洋一,小平行秀,高橋篤司","パス長制限付き点集合に対する配線木構成手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-4)",,"Vol. 109","No. 34","pp. 31-36",2009,May
"Yoshiaki Kurata,Yoichi Tomioka,Yukihide Kohira,Atsushi Takahashi","A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages",,"Proc. the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)",,,,"pp. 307-312",2009,Mar.
"Yoichi Tomioka,Atsushi Takahashi","A Semi-Monotonic Routing Method for Fanin Type Ball Grid Array Packages",,"Proc. the 2008 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2008)",,,,"pp. 1550-1553",2008,Dec.
"倉田芳明,富岡洋一,小平行秀,高橋篤司","最近傍ビア配置に基づく2層BGAパッケージ自動配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-55)",,"Vol. 108","No. 224","pp. 49-54",2008,Sept.
"佐藤直,富岡洋一,高橋篤司","2層BGAパッケージにおけるメッキ引き出し配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2007-154)",,"Vol. 107","No. 507","pp. 61-66",2008,Mar.
"Yoichi Tomioka,Atsushi Takahashi","Routability Driven Modification Method of Monotonic Via Assignment for 2-layer Ball Grid Array Packages",,"Proc. Asia and South Pacific Design Automation Conference 2008 (ASP-DAC 2008)",,,,"pp. 238-243",2008,Jan.
"Yoichi Tomioka,Atsushi Takahashi","Fast Monotonic Via Assignment Excluding Mold Gates for 2-Layer Ball Grid Array Packages",,"Proc. the 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2007)",,,,"pp. 192-197",2007,Oct.
"富岡洋一,高橋篤司","2層BGAパッケージにおける準順行ビア割り当て手法",,"DAシンポジウム2007 論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2007","No. 7","pp. 145-150",2007,Aug.
"Yoichi Tomioka,Atsushi Takahashi","Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E89-A","No. 12","pp. 3551-3559",2006,Dec.
"Yoichi Tomioka,Atsushi Takahashi","Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2006-76)",,"Vol. 106","No. 389","pp. 25-30",2006,Nov.
"富岡洋一,高橋篤司","BGAパッケージにおける配線混雑度を考慮した順行配線経路の自動生成手法",,"DAシンポジウム2006 論文集，情報処理学会シンポジウムシリーズ",,"Vol. 2006","No. 7","pp. 19-24",2006,July
"Yoichi Tomioka,Atsushi Takahashi","Monotonic Parallel and Orthogonal Routing for Single -Layer Ball Grid Array Packages",,"Proc. Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006)",,,,"pp. 642-647",2006,Jan.
"富岡洋一,高橋篤司","BGAパッケージにおける順行ピン割り当ての解析及び順行配線経路の自動生成",,"DAシンポジウム2005 論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2005","No. 9","pp. 237-242",2005,Aug.