"Bangan Liu,Huy Cu Ngo,Kengo Nakata,Wei Deng,Yuncheng Zhang,Junjun Qiu,Toru Yoshioka,Jun Emmei,Jian Pang,Tn Aravind,Haosheng Zhang,Dongsheng Yang,Hanli Liu,Teruki Someya,Atsushi Shirane,Kenichi Okada","A 0.4ps-Jitter -52dBc-Spur Synthesizable Injection-locked PLL with Self-clocked Non-overlap Update and Slope-balanced Sub-sampling BBPD",,"IEEE Solid-State Circuits Letters (SSC-L)",,"Vol. 2","No. 1","pp. 5-8",2019,Jan.
"Bangan Liu,Huy Cu Ngo,Kengo Nakata,Wei Deng,Yuncheng Zhang,Junjun Qiu,Toru Yoshioka,Jun Emmei,Haosheng Zhang,Jian Pang,Tn Aravind,Dongsheng Yang,Hanli Liu,Kenichi Okada,Akira Matsuzawa","A 1.2 ps-Jitter Fully-Synthesizable Fully-Calibrated Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique","IEEE Custom Integrated Circuits Conference (CICC)",,,,,,2018,Apr.
"Bangan Liu,Yun Wang,Jian Pang,Haosheng Zhang,Dongsheng Yang,Tn Aravind,Dae-Young Lee,SungTae Choi,Rui Wu,Kenichi Okada,Akira Matsuzawa","A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS",,"IEICE Transactions on Electronics",,"Vol. E101-C","No. 2","pp. 126-134",2018,Feb.
"Dongsheng Yang","A Study of Synthesizable Phase-Locked Loop for Clock Generation",,,,,,,2017,Mar.
"Dongsheng Yang","A STUDY OF SYNTHESIZABLE PHASE-LOCKED LOOP FOR CLOCK GENERATION",,,,,,,2017,Mar.
"Dongsheng Yang","A STUDY OF SYNTHESIZABLE PHASE-LOCKED LOOP FOR CLOCK GENERATION",,,,,,,2017,Mar.
"Tn Aravind,Wei Deng,Dongsheng Yang,Rui Wu,Kenichi Okada,Akira Matsuzawa","A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI",,"IEICE Transactions on Electronics",,"Vol. E100-C","No. 3","pp. 259-267",2017,Mar.
"Dongsheng Yang","A Study of Synthesizable Phase-Locked Loop for Clock Generation",,,,,,,2017,Mar.
"Dongsheng Yang,Wei Deng,Bangan Liu,Tn Aravind,Teerachot Siriburanon,Kenichi Okada,Akira Matsuzawa","An HDL-Synthesized Injection-Locked PLL Using LC-Based DCO for On-chip Clock Generation","IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC),",,,,,,2017,Jan.
"Dongsheng Yang,Wei Deng,Yuki Terashima,Teerachot Siriburanon,Tn Aravind,Toru Yoshioka,Kenichi Okada,Akira Matsuzawa","An LC-VCO based Synthesizable Injection-Locked PLL with an FoM of -250.3dB","IEEE European Solid-State Circuits Conference (ESSCIRC)",,,,,,2016,Sept.
"Dongsheng Yang,Tomohiro Ueno,Wei Deng,Kengo Nakata,Tn Aravind,Rui Wu,Kenichi Okada,Akira Matsuzawa","A 0.0055mm2 480?W Synthesizable PLL using Stochastic TDC in 28nm FDSOI",,"IEICE Transactions on Electronics","IEICE","Vol. E99-C","No. 6","pp. 632-640",2016,June
"Dongsheng Yang,Wei Deng,中田 憲吾,Teerachot Siriburanon,岡田 健一,松澤 昭","A Fully Synthesized Fractional-N IL-PLL Using Only Digital Library","電子情報通信学会 総合大会",,,,,"  C-12-9",2016,Mar.
"Dongsheng Yang,Wei Deng,Tharayil Narayanan Aravind,Kengo Nakata,Teerachot Siriburanon,Kenichi Okada,Akira Matsuzawa","An Automatic Place-and-Routed Two-Stage Fractional-N Injection-locked PLL Using Soft Injection","IEEE ACM Asia South Pacific Design Automation Conference",,,,,,2016,Jan.
"Dongsheng Yang,Wei Deng,Tn Aravind,Rui Wu,Bangan Liu,Kenichi Okada,Akira Matsuzawa","A Fully Synthesizable Injection-Locked PLL with Feedback Current Output DAC in 28nm FDSOI",,"IEICE Electronics Express","IEICE","Vol. 12","No. 15","pp. 1-11",2015,Aug.
"中田 憲吾,Wei Deng,Dongsheng Yang,上野 智大,THARAYILNAARAVIND,Teerachot Siriburanon,近藤 智史,岡田 健一,松澤 昭","注入同期を利用した自動合成配置配線可能なAll Digital Synthesizable PLL","電子情報通信学会 LSIとシステムのワークショップ",,,,,,2015,May
".Wei Deng,Dongsheng Yang,Aravind Tharayil Narayanan,,Kengo Nakata,Teerachot Siriburanon,Kenichi Okada,Akira Matsuzawa","A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique","IEEE SSCS Kansai Chapter ISSCC報告会",,,,,,2015,Mar.
"Wei Deng,Dongsheng Yang,Tn Aravind,Kengo Nakata,Teerachot Siriburanon,Kenichi Okada,Akira Matsuzawa","A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique","IEEE International Solid-State Circuits Conference (ISSCC),",,,,,,2015,Feb.
"Wei Deng,Dongsheng Yang,Tomohiro Ueno,Teerachot Siriburanon,Satoshi Kondo,Kenichi Okada,Akira Matsuzawa","A Fully Synthesizable All-digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-resolution Digital Varactor Using Gated Edge Injection Technique",,"IEEE Journal of Solid-State Circuits",,"Vol. 50","No. 1","pp. 68-80",2015,Jan.
"Dongsheng Yang,Wei Deng,Tomohiro Ueno,Teerachot Siriburanon,Satoshi Kondo,Kenichi Okada,Akira Matsuzawa","An HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC","IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC)",,,,,,2015,Jan.
"AravindTharayil Narayanan,Wei Deng,Yang Dongsheng,Wu Rui,Kenichi Okada,Akira Matsuzawa","A 0.011 mm2 PVT‐Robust Fully‐Synthesizable CDR with a Data Rate of 10.05 Gb/S Using Injection‐","IEEE Asian Solid-State Circuits Conference (A-SSCC)",,,,,,2014,Nov.
"Wei Deng,Dongsheng Yang,Tomohiro Ueno,Teerachot Siriburanon,Satoshi Kondo,Kenichi Okada,Akira Matsuzawa","A 0.0066mm2 780?W Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique","IEEE SSCS Japan Chapter ISSCC報告会",,,,,,2014,May
"Dongsheng Yang,Wei Deng,Teerachot Siriburanon,岡田 健一,松澤 昭","A 0.4ps/bit Digitally-controlled Varactor for a Fully Synthesizable DCO","電子情報通信学会 総合大会",,,"  C-12-36",,,2014,Mar.
"Wei Deng,Dongsheng Yang,Tomohiro Ueno,Teerachot Siriburanon,Kenichi Okada,Akira Matsuzawa","Digitally Synthesized PLL with a DAC and Phase-Coupled Oscillator using Standard Cells Only","電子情報通信学会 総合大会",,,"  C-12-30",,,2014,Mar.
"Wei Deng,Dongsheng Yang,Tomohiro Ueno,Teerachot Siriburanon,Satoshi Kondo,Kenichi Okada,Akira Matsuzawa","A 0.0066-mm2 780-?W Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique","IEEE International Solid-State Circuits Conference (ISSCC)",,,,,"pp. 266-267",2014,Feb.