"Toshio Endo,Hiroko Midorikawa,Yukinori Sato.","Software Technology that Deals with Deeper Memory Hierarchy in Post-petascale Era.","JST/CREST International Symposium on Post Petascale System Software (ISP2S2-2017)",,,,,,2017,Dec.
"Yukinori Sato,Toshio Endo","An Accurate Simulator of Cache-line Conflicts to Exploit the Underlying Cache Performance","In Proceedings of 23rd International European Conference on Parallel and Distributed Computing (Euro-par 2017)",,,,,,2017,Aug.
"幸 朋矢,佐藤 幸紀,遠藤 敏夫","Polyhedralコンパイラを用いたタイリングパラメータ自動調整ツールのメニーコア環境での評価","並列/分散/協調処理に関するサマーワークショップ(SWoPP2017)",,,,,,2017,July
"Yukinori Sato,Tomoya Yuki,Toshio Endo","ExanaDBT: A Dynamic Compilation System for Transparent Polyhedral Optimizations at Runtime","In Proceedings of ACM International Conference on Computing Frontiers 2017",,,"  10pages",,,2017,May
"佐藤幸紀,幸朋矢,遠藤敏夫","透過的メモリ階層チューニングのための動的バイナリ変換機構の設計と開発","情報処理学会研究報告","2016-ARC-216 No.35",,,,,2017,Jan.
"佐藤真平,佐藤幸紀,遠藤敏夫","ステンシル計算コードの性能とメモリレイアウトの関係性について","並列/分散/協調処理に関するサマーワークショップ（SWoPP2016）","情報処理学会研究報告",,"Vol. 2016-HPC-155","No. 37",,2016,Aug.
"Yukinori Sato,Toshio Endo.","Dynamic Compilation for Transparent Data Locality Analysis and Memory Subsystem Tuning .","The International Workshop on Architectural and Micro-Architectural Support for Dynamic Optimization (AMAS-DO), In conjunction with CGO 2016",,,,,,2016,Mar.
"Shimpei Sato,Yukinori Sato,Toshio Endo","A Cache-aware Temporal Blocking Method for 3D Stencil Computation","3rd International Workshop on High-Performance Stencil Computations (HiStencils 2016), In conjunction with HiPEAC 2016",,,,,,2016,Jan.
"Yukinori Sato,Toshio Endo","Consolidating memory locality information obtained from static and dynamic analysis of code for performance tuning in source code","2nd Annual Meeting on Advanced Computing System and Infrastructure (ACSI2016), ポスターセッション",,,,,,2016,Jan.
"Yukinori Sato,Shimpei Sato,Toshio Endo","Exana: An Execution-driven Application Analysis Tool for Assisting Productive Performance Tuning","In Proceedings of The Second Workshop on Software Engineering for Parallel Systems (SEPS), in conjunction with ACM SPLASH 2015",,,,,,2015,Oct.
"Shimpei Sato,Yukinori Sato,Toshio Endo","Investigating Potential Performance Benefits of Memory Layout Optimization based on Roofline Model","In Proceedings of The Second Workshop on Software Engineering for Parallel Systems (SEPS), in conjunction with ACM SPLASH 2015",,,,,,2015,Oct.
"佐藤幸紀,佐藤真平,遠藤敏夫","CPU性能チューニングを支援するアプリケーション解析ツールExanaのデモ","電子情報通信学会 コンピュータシステム研究会 萌芽的コンピュータシステム研究展示会",,,,,,2015,Oct.
"佐藤真平,佐藤幸紀,遠藤敏夫","テンポラルブロッキングを適用したステンシル計算コードのSIMD化とルーフラインモデルを用いた性能解析","情報処理学会 第151回ハイパフォーマンスコンピューテング研究会",,,,,,2015,Sept.
"佐藤真平,佐藤幸紀,遠藤敏夫","ルーフラインモデルによる性能幅推定とステンシル計算コードにおけるメモリレイアウト最適化による性能最大化","並列/分散/協調処理に関するサマーワークショップ（SWoPP2015）","情報処理学会研究報告",,"Vol. 2015-ARC-216","No. 32","pp. 1-6",2015,Aug.
"佐藤幸紀,遠藤敏夫","実行駆動型キャッシュシミュレーションおよびメモリ参照特性解析におけるオーバーヘッドの評価","並列/分散/協調処理に関するサマーワークショップ(SWoPP2015)， 情報処理学会研究報告, 2015-ARC-216 No.31, 7pages",,,,,,2015,Aug.
"佐藤幸紀,佐藤真平","メモリ階層性能シミュレータを用いたCPU単体性能チューニング","ハイパフォーマンスコンピューティングと計算科学シンポジウム","ハイパフォーマンスコンピューティングと計算科学シンポジウム論文集",,"  2015",,"  100-100",2015,May