"Wenqian Wang,Junjun Qiu,白根 篤史,岡田 健一","A Comparator-based Gain Boosted PD Design for 32kHz Reference Oversampling PLL","電子情報通信学会 総合大会",,,,,,2024,Mar.
"Dingxin Xu,Zezheng Liu,Yifeng Kuai,Hongye Huang,Yuncheng Zhang,Zheng Sun,Bangan Liu,Wenqian Wang,Yuang Xiong,Junjun Qiu,Waleed Madany,Yi Zhang,Ashbir Aviat Fadila,Atsushi Shirane,Kenichi Okada","A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter","IEEE International Solid-State Circuits Conference?(ISSCC)",,,,,,2024,Feb.
"Waleed Madany,Yuncheng Zhang,Ashbir Aviat Fadila,Hongye Huang,Junjun Qiu,Atsushi Shirane,Kenichi Okada","A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path","IEEE European Solid-State Circuits Conference?(ESSCIRC)",,,,,,2023,Sept.
"Yuncheng Zhang,Zheng Sun,Bangan Liu,Junjun Qiu,Dingxin Xu,Yi Zhang,Xi Fu,Dongwon You,Hongye Huang,Waleed Madany,Ashbir Aviat Fadila,Zezheng Liu,Wenqian Wang,Yuang Xiong,Atsushi Shirane,Kenichi Okada","A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit DSM and Transformer Combined FIR","IEEE SSCS Japan Chapter VLSI Circuits報告会",,,,,,2023,July
"Dingxin Xu,Yuncheng Zhang,Hongye Huang,Zheng Sun,Bangan Liu,Ashbir Aviat Fadila,Junjun Qiu,Zezheng Liu,Wenqian Wang,Yuang Xiong,Waleed Madany,Atsushi Shirane,Kenichi Okada","A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference","IEEE Custom Integrated Circuits Conference?(CICC)",,,,,,2023,Apr.
"Junjun Qiu,Wenqian Wang,Zheng Sun,Bangan Liu,Yuncheng Zhang,Dingxin Xu,Hongye Huang,Ashbir Aviat Fadila,Zezheng Liu,Waleed Madany,Yuang Xiong,Atsushi Shirane,Kenichi Okada","A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration","IEEE International Solid-State Circuits Conference (ISSCC)",,,,,,2023,Feb.
"Yuncheng Zhang,Bangan Liu,Teruki Someya,Rui Wu,Junjun Qiu,Atsushi Shirane,Kenichi Okada","A 0.37mm2 Fully-IntegratedWide Dynamic Range Sub-GHz Receiver Front-end without Off-chip Matching Components," IEICE Transactions on Electronics",,"IEICE Transactions on Electronics",,"Vol. E105-C","No. 7","pp. 334-342",2022,July
"Junjun Qiu","A Study of Fractional-N Oversampling Frequency Synthesizers Using Digital-Assisted Calibration",,,,,,,2022,June
"Junjun Qiu","A Study of Fractional-N Oversampling Frequency Synthesizers Using Digital-Assisted Calibration",,,,,,,2022,June
"Junjun Qiu","A Study of Fractional-N Oversampling Frequency Synthesizers Using Digital-Assisted Calibration",,,,,,,2022,June
"Junjun Qiu,Bangan Liu,Atsushi Shirane,Kenichi Okada","A Low-power Digital Baseband Circuit for GMSK Demodulation in Sub-GHz Application",,"IEICE Electronics Express",,"Vol. 19","No. 12","pp. 1-6",2022,June
"Junjun Qiu","A Study of Fractional-N Oversampling Frequency Synthesizers Using Digital-Assisted Calibration",,,,,,,2022,June
"Yuncheng Zhang,Bangan Liu,Junjun Qiu,Atsushi Shirane,Kenichi Okada","A 1-bit-DSM-based Digital Polar Power Amplifier Supporting 1024-QAM",,"IEEE Solid-State Circuits Letters (SSC-L)",,"Vol. 5",,"pp. 130-133",2022,May
"Junjun Qiu,Jian Pang,Bangan Liu,Xueting Luo,Yun Wang,Yuncheng Zhang,Atsushi Shirane,Kenichi Okada","A CMOS 24-30 GHz Low-Phase-Variation Variable Gain Amplifier Design for 5G New Radio",,"IEEE Solid-State Circuits Letters (SSC-L)",,"Vol. 5",,"pp. 146-149",2022,May
"Yun Wang,Dongwon You,Xi Fu,Takeshi Nakamura,Ashbir Aviat Fadila,Teruki Someya,Atsuhiro Kawaguchi,Junjun Qiu,Jian Pang,Kiyoshi Yanagisawa,Bangan Liu,Yuncheng Zhang,Haosheng Zhang,Rui Wu,Shunichiro Masaki,Daisuke Yamazaki,Atsushi Shirane,Kenichi Okada","A Ka-Band SATCOM Transceiver in 65-nm CMOS with High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Termina",,"IEEE Journal of Solid-State Circuits","IEEE","Vol. 57","No. 2","pp. 356-370",2022,Feb.
"Junjun Qiu,Zheng Sun,Bangan Liu,Wenqian Wang,Dingxin Xu,Hans Herdian,Hongye Huang,Yuncheng Zhang,Yun Wang,Jian Pang,Hanli Liu,Masaya Miyahara,Atsushi Shirane,Kenichi Okada","A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth",,"IEEE Journal of Solid-State Circuits","IEEE","Vol. 56","No. 12","pp. 3741-3755",2021,Dec.
". Zheng Sun,Dingxin Xu,Junjun Qiu,Zezheng Liu,Yuncheng Zhang,Hongye Huang,Hanli Liu,Bangan Liu,Zheng Li,Jian Pang,Atsushi Shirane,Kenichi Okada","A 0.25mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration","IEEE European Solid-State Circuits Conference (ESSCIRC)",,,,,,2021,Sept.
"Junjun Qiu,Zheng Sun,Bangan Liu,Wenqian Wang,Dingxin Xu,Hans Herdian,Hongye Huang,Yuncheng Zhang,Yun Wang,Atsushi Shirane,Kenichi Okada","200kHzループ帯域幅の32kHzリファレンス2.4GHzフラクショナルNオーバーサンプリングPLL","電子情報通信学会 LSIとシステムのワークショップ",,,,,,2021,May
"Zheng Sun,Dingxin Xu,Junjun Qiu,Atsushi Shirane,Kenichi Okada","A 0.38mm2 BLE Transmitter with 29% System Efficiency Using Duty-Cycled Edge-Timing Calibration in 65nm CMOS","IEEE International Solid-State Circuits Conference (ISSCC)",,,,,,2021,Feb.
"Junjun Qiu,Zheng Sun,Bangan Liu,Wenqian Wang,Dingxin Xu,Hans Herdian,Hongye Huang,Yuncheng Zhang,Yun Wang,Atsushi Shirane,Kenichi Okada","A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth","IEEE International Solid-State Circuits Conference (ISSCC)",,,,,,2021,Feb.
"Jian Pang,Zheng Li,Ryo Kubozoe,Xueting Luo,Rui Wu,Yun Wang,Dongwon You,Ashbir Aviat Fadila,Rattanan Saengchan,Takeshi Nakamura,Joshua Alvin,Daiki Matsumoto,Bangan Liu,Aravind Tharayil Narayanan,Junjun Qiu,Hanli Liu,Zheng Sun,Hongye Huang,Korkut Kaan Tokgoz,K. Motoi,N. Oshima,S. Hori,K. Kunihiro,T. Kaneko,A. Shirane,K. Okada","A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR",,"IEEE Journal of Solid-State Circuits",,"Vol. 55","No. 9","pp. 2371-2386",2020,Sept.
"Yun Wang,Rui Wu,Jian Pang,Dongwon You,Ashbir Aviat Fadila,Rattanan Saengchan,Xi Fu,Daiki Matsumoto,Takeshi Nakamura,Ryo Kubozoe,Masaru Kawabuchi,Bangan Liu,Haosheng Zhang,Junjun Qiu,Hanli Liu,Naoki Oshima,Keiichi Motoi,Shinichi Hori,Kazuaki Kunihiro,Tomoya Kaneko,Atsushi Shirane,Kenichi Okada","A 39-GHz 64-Element Phased-Array Transceiver with Built-in Phase and Amplitude Calibration for Large-Array 5G NR in 65-nm CMOS",,"IEEE Journal of Solid-State Circuits",,"Vol. 55","No. 5","pp. 1249-1269",2020,May
"Bangan Liu,Yuncheng Zhang,Junjun Qiu,Hongye Huang,Zheng Sun,Dingxin Xu,Haosheng Zhang,Yun Wang,Jian Pang,Zheng Li,Xi Fu,Atsushi Shirane,Hitoshi Kurosu,Yoshinori Nakane,Shunichiro Masaki,Kenichi Okada","A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS",,"IEEE Solid-State Circuits Letters",,"Vol. 3",,"pp. 34-37",2020,Jan.
"Junjun Qiu,Bangan Liu,Yuncheng Zhang,染谷 晃基,白根 篤史,岡田 健一","Digital Baseband Design for Sub-GHz Transceiver","電子情報通信学会 ソサイエティ大会",,,,,,2019,Sept.
"Bangan Liu,Yuncheng Zhang,Junjun Qiu,Wei Deng,Zule Xu,Haosheng Zhang,Jian Pang,Yun Wang,Rui Wu,染谷 晃基,白根 篤史,岡田 健一","A 21.7% System Power Efficiency Fully-Synthesizable Transmitter for sub-GHz IoT Applications","電子情報通信学会 ソサイエティ大会",,,,,,2019,Sept.
"Yun Wang,Rui Wu,Jian Pang,Dongwon You,Ashbir Aviat Fadila,Rattanan Saengchan,Xi Fu,Daiki Matsumoto,Takeshi Nakamura,Ryo Kubozoe,Masaru Kawabuchi,Bangan Liu,Haosheng Zhang,Junjun Qiu,Hanli Liu,Naoki Oshima,Keiichi Motoi,Shinichi Hori,Kazuaki Kunihiro,Tomoya Kaneko,Atsushi Shirane,Kenichi Okada","A 39GHz Phased-Array CMOS Transceiver with Built-in Calibration for Large-Array 5G NR","IEEE Radio Frequency Integrated Circuits Symposium (RFIC)",,,,,,2019,June
"Bangan Liu,Yuncheng Zhang,Junjun Qiu,Wei Deng,Zule Xu,Haosheng Zhang,Jian Pang,Yun Wang,Rui Wu,Teruki Someya,Atsushi Shirane,Kenichi Okada","An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator Based Frequency Synthesizer and Digital Background EVM Calibration","IEEE Custom Integrated Circuits Conference (CICC)",,,,,,2019,Apr.
"Junjun Qiu,Bangan Liu,Yuncheng Zhang,Teruki Someya,Atsushi Shirane,Kenichi Okada","A Fully-synthesizable Symbol Timing Recovery Circuit for Low-Power Wireless Receiver","電子情報通信学会 集積回路研究会",,,"Vol. ICD2018-113","No. 507","pp. 73-76",2019,Mar.
"Yuncheng Zhang,Bangan Liu,Junjun Qiu,Teruki Someya,Atsushi Shirane,Kenichi Okada","A Low-Power Area Efficient Sub-GHz IoT Receiver without Off-Chip Components","電子情報通信学会 集積回路研究会",,,"Vol. ICD2018-114",,"pp. 77-80",2019,Mar.
"Bangan Liu,Yuncheng Zhang,Junjun Qiu,Teruki Someya,Atsushi Shirane,Kenichi Okada","A Fully-synthesizable Ring Oscillator Based Frequency Synthesizer for Sub-GHz IoT Application","電子情報通信学会 集積回路研究会",,,"Vol. ICD2018-112","No. 507","pp. 67-71",2019,Mar.
"Jian Pang,Zheng Li,窪添 諒,Xueting Luo,Rui Wu,Yun Wang,Dongwon You,Ashbir Aviat Fadila,Rattanan Saengchan,中村 岳資,Joshua Alvin,松本 大輝,THARAYILNAARAVIND,Bangan Liu,Junjun Qiu,Hanli Liu,Zheng Sun,Hongye Huang,白根 篤史,岡田 健一","双方向動作可能な5GNR二偏波MIMO対応28GHz帯CMOSフェーズドアレイ無線機","電子情報通信学会 集積回路研究会",,,"Vol. ICD2018-106","No. 507","pp. 31-35,",2019,Mar.
"Bangan Liu,Huy Cu Ngo,Kengo Nakata,Wei Deng,Yuncheng Zhang,Junjun Qiu,Toru Yoshioka,Jun Emmei,Jian Pang,Tn Aravind,Haosheng Zhang,Dongsheng Yang,Hanli Liu,Teruki Someya,Atsushi Shirane,Kenichi Okada","A 0.4ps-Jitter -52dBc-Spur Synthesizable Injection-locked PLL with Self-clocked Non-overlap Update and Slope-balanced Sub-sampling BBPD",,"IEEE Solid-State Circuits Letters (SSC-L)",,"Vol. 2","No. 1","pp. 5-8",2019,Jan.
"Bangan Liu,Huy Cu Ngo,Wei Deng,Yuncheng Zhang,Junjun Qiu,Kengo Nakata,Teruki Someya,Atsushi Shirane,Kenichi Okada","A 1.2 ps-Jitter Fully-Synthesizable DTC-based Fractional-N Injection-Locked PLL using True Arbitrary Nonlinearity Calibration","電子情報通信学会 ソサイエティ大会",,,,,,2018,Sept.
"Bangan Liu,Huy Cu Ngo,Yuncheng Zhang,Junjun Qiu,中田 憲吾,白根 篤史,岡田 健一","A Fully-Synthesizable Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique","電子情報通信学会 LSIとシステムのワークショップ",,,,,,2018,May
"Bangan Liu,Huy Cu Ngo,Kengo Nakata,Wei Deng,Yuncheng Zhang,Junjun Qiu,Toru Yoshioka,Jun Emmei,Haosheng Zhang,Jian Pang,Tn Aravind,Dongsheng Yang,Hanli Liu,Kenichi Okada,Akira Matsuzawa","A 1.2 ps-Jitter Fully-Synthesizable Fully-Calibrated Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique","IEEE Custom Integrated Circuits Conference (CICC)",,,,,,2018,Apr.
"Junjun Qiu,Bangan Liu,Yuncheng Zhang,Kenichi Okada,Akira Matsuzawa","An ultra-low-power digital GMSK demodulator for sub-GHz IoT applications","電子情報通信学会 ソサイエティ大会",,,,,"  C-12-6",2017,Sept.