"Yuang Xiong,Dingxin Xu,Yuncheng Zhang,白根 篤史,岡田 健一","A Compact Class-F LC Oscillator with Multi-resonance Mode for Low Jitter PLL Designs","電子情報通信学会 総合大会",,,,,,2024,Mar.
"Daxu Zhang,Yuncheng Zhang,Hongye Huang,Dingxin Xu,白根 篤史,岡田 健一","A Multi-Phase Frequency Synthesizer with Injection-Locking Ring Oscillator","電子情報通信学会 総合大会",,,,,,2024,Mar.
"Dingxin Xu,Zezheng Liu,Yifeng Kuai,Hongye Huang,Yuncheng Zhang,Zheng Sun,Bangan Liu,Wenqian Wang,Yuang Xiong,Junjun Qiu,Waleed Madany,Yi Zhang,Ashbir Aviat Fadila,Atsushi Shirane,Kenichi Okada","A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter","IEEE International Solid-State Circuits Conference?(ISSCC)",,,,,,2024,Feb.
"Yuncheng Zhang,Zheng Sun,Bangan Liu,Junjun Qiu,Dingxin Xu,Yi Zhang,Xi Fu,Dongwon You,Hongye Huang,Waleed Madany,Ashbir Aviat Fadila,Zezheng Liu,Wenqian Wang,Yuang Xiong,Atsushi Shirane,Kenichi Okada","A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit DSM and Transformer Combined FIR","IEEE SSCS Japan Chapter VLSI Circuits報告会",,,,,,2023,July
"Dingxin Xu,Yuncheng Zhang,Hongye Huang,Zheng Sun,Bangan Liu,Ashbir Aviat Fadila,Junjun Qiu,Zezheng Liu,Wenqian Wang,Yuang Xiong,Waleed Madany,Atsushi Shirane,Kenichi Okada","A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference","IEEE Custom Integrated Circuits Conference?(CICC)",,,,,,2023,Apr.
"Junjun Qiu,Wenqian Wang,Zheng Sun,Bangan Liu,Yuncheng Zhang,Dingxin Xu,Hongye Huang,Ashbir Aviat Fadila,Zezheng Liu,Waleed Madany,Yuang Xiong,Atsushi Shirane,Kenichi Okada","A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration","IEEE International Solid-State Circuits Conference (ISSCC)",,,,,,2023,Feb.
"Dingxin Xu,Zheng Sun,Hongye Huang,白根 篤史,岡田 健一","A Current-Reused Ring Oscillator with Edge-Combining Technique for BLE TX","電子情報通信学会 集積回路研究会",,,,,,2022,Dec.
"Junjun Qiu,Zheng Sun,Bangan Liu,Wenqian Wang,Dingxin Xu,Hans Herdian,Hongye Huang,Yuncheng Zhang,Yun Wang,Jian Pang,Hanli Liu,Masaya Miyahara,Atsushi Shirane,Kenichi Okada","A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth",,"IEEE Journal of Solid-State Circuits","IEEE","Vol. 56","No. 12","pp. 3741-3755",2021,Dec.
". Zheng Sun,Dingxin Xu,Junjun Qiu,Zezheng Liu,Yuncheng Zhang,Hongye Huang,Hanli Liu,Bangan Liu,Zheng Li,Jian Pang,Atsushi Shirane,Kenichi Okada","A 0.25mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration","IEEE European Solid-State Circuits Conference (ESSCIRC)",,,,,,2021,Sept.
"Zheng Sun,Hanli Liu,Dingxin Xu,Hongye Huang,Bangan Liu,Zheng Li,Jian Pang,Teruki Someya,Atsushi Shirane,Kenichi Okada","A Low-Jitter Injection-Locked Clock Multiplier Using 97-?W Transformer-Based VCO with 18-kHz Flicker Noise Corner",,"IEICE Transactions on Electronics",,"Vol. E104-C","No. 7","pp. 289-299",2021,July
"Junjun Qiu,Zheng Sun,Bangan Liu,Wenqian Wang,Dingxin Xu,Hans Herdian,Hongye Huang,Yuncheng Zhang,Yun Wang,Atsushi Shirane,Kenichi Okada","200kHzループ帯域幅の32kHzリファレンス2.4GHzフラクショナルNオーバーサンプリングPLL","電子情報通信学会 LSIとシステムのワークショップ",,,,,,2021,May
"Zheng Sun,Dingxin Xu,Junjun Qiu,Atsushi Shirane,Kenichi Okada","A 0.38mm2 BLE Transmitter with 29% System Efficiency Using Duty-Cycled Edge-Timing Calibration in 65nm CMOS","IEEE International Solid-State Circuits Conference (ISSCC)",,,,,,2021,Feb.
"Junjun Qiu,Zheng Sun,Bangan Liu,Wenqian Wang,Dingxin Xu,Hans Herdian,Hongye Huang,Yuncheng Zhang,Yun Wang,Atsushi Shirane,Kenichi Okada","A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth","IEEE International Solid-State Circuits Conference (ISSCC)",,,,,,2021,Feb.
"Zheng Sun,Dingxin Xu,Hongye Huang,Zheng Li,Hanli Liu,Bangan Liu,Jian Pang,Teruki Someya,Atsushi Shirane,Kenichi Okada","A Compact TF-based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications",,"IEICE Transactions on Electronics",,"Vol. E103-C","No. 10","pp. 505-513",2020,Oct.
"Bangan Liu,Yuncheng Zhang,Junjun Qiu,Hongye Huang,Zheng Sun,Dingxin Xu,Haosheng Zhang,Yun Wang,Jian Pang,Zheng Li,Xi Fu,Atsushi Shirane,Hitoshi Kurosu,Yoshinori Nakane,Shunichiro Masaki,Kenichi Okada","A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS",,"IEEE Solid-State Circuits Letters",,"Vol. 3",,"pp. 34-37",2020,Jan.
"Zheng Sun,Hanli Liu,Dingxin Xu,Hongye Huang,Bangan Liu,Zheng Li,Jian Pang,Teruki Someya,Atsushi Shirane,Kenichi Okada","A 78fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO","IEEE European Solid-State Circuits Conference (ESSCIRC)",,,,,,2019,Sept.
"Dingxin Xu,Zheng Sun,Hongye Huang,染谷 晃基,白根 篤史,岡田 健一","A Time-Amplifier Gain Calibration Technique for ADPLL","電子情報通信学会 ソサイエティ大会",,,,,,2019,Sept.
"Zheng Sun,Dingxin Xu,Hongye Huang,染谷 晃基,白根 篤史,岡田 健一","A 78fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO","電子情報通信学会 ソサイエティ大会",,,,,,2019,Sept.
"Hongye Huang,Hanli Liu,Zheng Sun,Dingxin Xu,染谷 晃基,白根 篤史,岡田 健一","A 2.4GHz Low-Power Subsampling/Sampling-Mixed Fractional-N All-Digital PLL","電子情報通信学会 ソサイエティ大会",,,,,,2019,Sept.
"Dingxin Xu,Hanli Liu,Zheng Sun,Hongye Huang,Wei Deng,Teerachot Siriburanon,Jian Pang,Yun Wang,Rui Wu,染谷 晃基,白根 篤史,岡田 健一","A 265-?W Fractional-N Digital PLL with Switching Subsampling/Sampling Feedback","電子情報通信学会 LSIとシステムのワークショップ",,,,,,2019,May
"Dingxin Xu","A Study of Fractional Spur Suppression Techniques in Digital Phase-Locked Loops",,,,,,,,
"Dingxin Xu","A Study of Fractional Spur Suppression Techniques in Digital Phase-Locked Loops",,,,,,,,