"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Masayuki Shimoda,Shimpei Sato","GUINNESS: A GUI based Binarized Deep Neural Network Framework for Software Programmers",,"IEICE Transactions on Information and Systems",,"Vol. E102-D","No. 5","pp. 1003-1011",2019,May
"Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara","A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor","The 48th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2018)",,,,,"pp. 174-179",2018,May
"Kota Ando,Kodai Ueyoshi,Kentaro Orimo,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Shinya Takamaeda-Yamazaki,Masayuki Ikebe,Tetsuya Asai,Tadahiro Kuroda,Masato Motomura","BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W",,"IEEE Journal of Solid-State Circuits",,"Vol. 53","No. 4","pp. 983-994",2018,Apr.
"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Shimpei Sato","A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA","The 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018)",,,,,,2018,Feb.
"米川晴義,佐藤真平,中原啓貴","重み3値入出力2値ディープニューラルネットワークの学習と組込みプロセッサ実現について","第31回多値論理とその応用研究会",,,,,,2018,Jan.
"宇山拓夢,藤井智也,米川晴義,佐藤真平,中原啓貴","Intel OpenCLを用いたディープニューラルネットワークのFPGA実現に関して",,"電子情報通信学会技術研究報告",,"vol. 117","no. 379","pp. 13-18",2018,Jan.
"Hiroki Nakahara,Haruyoshi Yonekawa,Shimpei Sato","An Object Detector based on Multiscale Sliding Window Search using a Fully Pipelined Binarized CNN on an FPGA","The International Conference on Field-Programmable Technology (FPT 2017)",,,,,"pp. 168-175",2017,Dec.
"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Masayuki Shimoda,Shimpei Sato","GUINNESS: A GUI based neural network synthesizer for an FPGA","The 27th International Conference on Field-programmable Logic and Applications (FPL 2017)",,,,,,2017,Sept.
"Kota Ando,Kodai Ueyoshi,Kazutoshi Hirose,Kentaro Orimo,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Masayuki Ikebe,Shinya Takamaeda-Yamazaki,Tetsuya Asai,Tadahiro Kuroda,Masato Motomura","In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks","The 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017)",,,,,"pp. 116-119",2017,Aug.
"Kota Ando,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Masato Motomura","BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS","2017 Symposia on VLSI Technology and Circuits",,,,,,2017,June
"Haruyoshi Yonekawa,Hiroki Nakahara","An On-chip Memory Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA","24th Reconfigurable Architectures Workshop (RAW 2017)",,,,,,2017,May
"Hiroki Nakahara,Haruyoshi Yonekawa,Hisashi Iwamoto,Masato Motomura","A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA","International Symposium on Field-Programmable Gate Array (FPGA2017)",,,,,,2017,Feb.
"米川 晴義,中原 啓貴,本村 真人","ディープニューラルネットワークの2値化と3値化の比較","多値論理研究会",,,,,,2017,Jan.
"米川晴義,中原啓貴,本村真人","電力性能効率に優れた二値化ディープニューラルネットワークのFPGA実装","電子情報通信学会リコンフィギャラブルシステム研究会",,,,,,2017,Jan.
"Hiroki Nakahara,Haruyoshi Yonekawa,Tsutomu Sasao,Hisashi Iwamoto,Masato Motomura","A Memory-Based Realization of a Binarized Deep Convolutional Neural Network","The International Conference on Field-Programmable Technology (FPT 2016),",,,,,,2016,Dec.