論文

• Yun Wang, Bangan Liu, Rui Wu, Hanli Liu, Tn Aravind, Jian Pang, Ning Li, Toru Yoshioka, Yuki Terashima, Haosheng Zhang, Dexian Tang, Makihiko Katsuragi, Daeyoung Lee, Sungtae Choi, Kenichi Okada, Akira Matsuzawa. A 60-GHz 3.0Gb/s Spectrum Efficient BPOOK Transceiver for Low-power Short-range Wireless in 65-nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 5, pp. 1363-1374, May 2019.
• Jian Pang, Shotaro Maki, Seitaro Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Tn Aravind, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada. A 50.1Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay with Calibration of LO Feed-Through and I/Q Imbalance, IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 5, pp. 1375-1390, May 2019.

国際会議発表 (査読有り)

• Yun Wang, Bangan Liu, Hanli Liu, Tn Aravind, Jian Pang, Ning Li, Toru Yoshioka, Yuki Terashima, Haosheng Zhang, Dexian Tang, Makihiko Katsuragi, Daeyoung Lee, Sungtae Choi, Rui Wu, Kenichi Okada, Akira Matsuzawa. A 100mW 3.0Gb/s Spectrum Efficient 60GHz Bi-Phase OOK CMOS Transceiver, IEEE Symposium on VLSI Circuits, June 2017.
• Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa. A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO, EEE International Solid-State Circuits Conference (ISSCC),, Feb. 2017.
• Dongsheng Yang, Wei Deng, Yuki Terashima, Teerachot Siriburanon, Tn Aravind, Toru Yoshioka, Kenichi Okada, Akira Matsuzawa. An LC-VCO based Synthesizable Injection-Locked PLL with an FoM of -250.3dB, IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2016.
• Tharayil Narayanan Aravind, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa. A Noise Reduction Technique for Divider-Less Fractional-N Frequency Synthesizer using Phase-Interpolation Technique, IEEE ACM Asia South Pacific Design Automation Conference, Jan. 2016.
• Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Yuki Terashima, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with an FoM of -246dBc/Hz, IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2015.

国内会議発表 (査読なし・不明)

• Yuncheng Zhang, Ngo Huy Cu, 中田 憲吾, 吉岡 透, Yuki Terashima, Bangan Liu, 岡田 健一, 松澤 昭. An Ultra-Low-Power Synthesizable Digitally Controlled Oscillator, 電子情報通信学会 総合大会, C-12, Mar. 2017.
• Bangan Liu, Ngo Huy Cu, 中田 憲吾, 吉岡 透, Yuki Terashima, 岡田 健一, 松澤 昭. A Study of Injection-locking PLL Phase Calibration with Symmetrical Phase Detector and Multiplexer, 電子情報通信学会 総合大会, C-12, Mar. 2017.
• Ngo Huy Cu, 中田 憲吾, 吉岡 透, 寺嶋友樹, 岡田 健一, 松澤 昭. 周波数逓倍器による注入同期PLL の雑音抑制手法, 電子情報通信学会 総合大会, C-12, Mar. 2017.
• Ngo Huy Cu, 中田 憲吾, 吉岡 透, Yuki Terashima, 岡田 健一, 松澤 昭. A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO, 電子情報通信学会 アナログRF研究会, Vol. RF2017-3, Mar. 2017.
• Ngo Huy Cu, 中田 憲吾, 吉岡 透, Yuki Terashima, 岡田 健一, 松澤 昭. A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO, IEEE SSCS Japan Chapter ISSCC報告会, Feb. 2017.
• Ngo Huy Cu, 寺嶋友樹, 吉岡 透, 岡田 健一, 松澤 昭. 自動配置配線可能なLC型DCOの解析, 電子情報通信学会 ソサイエティ大会, C-12-7, Sept. 2016.
• 寺嶋 友樹, Teerachot Siriburanon, 岡田 健一, 松澤 昭. 2.25分周器に関する検討, 電子情報通信学会 ソサイエティ大会, C-12-17, Sept. 2014.

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