論文

• Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector, IEICE Transactions on Electronics, Vol. E102-C, No. 7, pp. 520-529, July 2019.

国際会議発表 (査読有り)

• Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A 2GHz 3.1mW Type-I Digital Ring-Based PLL, IEEE European Solid-State Circuits Conference (ESSCIRC),, Sept. 2016.
• Anugerah Firdauzi, Zule Xu, Masaya Nohara (Miyahara), Akira Matsuzawa. A 74.5 dB SNDR 1 MHz Bandwidth 1.17 mW Delta-Sigma Time to Digital Converter Using Charge-Pump and SAR ADC, IEEE International Symposium on Circuits ans Systems 2016, May 2016.

国内会議発表 (査読なし・不明)

• Anugerah Firdauzi, Zule Xu, Masaya Nohara (Miyahara), Akira Matsuzawa. A Low-Power Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Charge-Pump and SAR ADC, IEICE Technical Committee on Integrated Circuit and Devices (ICD), Aug. 2016.
• Anugerah Firdauzi, Xu Zule, Masaya Miyahara, Akira Matsuzawa. Delta-Sigma Time to Digital Converter Using Charge Pump and SAR ADC, 電子情報通信学会 総合大会, Mar. 2015.

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