@article{CTT100457332,
  author = {Bin Zhou and Tomohiro Yoneda and Chris Myers},
  title = {Framework of Timed Trace Theoretic Verification Revisited},
  journal = {Proc. of 10th Asian Test Symposium},
  year = 2001,
}

@article{CTT100457325,
  author = {Eric Mercer and Chris Myers and Tomohiro Yoneda},
  title = {Improved poset timing analysis in timed Petri nets},
  journal = {Proc. of The 10th Workshop on Synthesis And System Integration of Mixed Technologies},
  year = 2001,
}

@article{CTT100457324,
  author = {Tomohiro Yoneda and Eric Mercer and Chris Myers},
  title = {Modular Synthesis of Timed Circuits using Partial Order Reduction},
  journal = {Proc. of The 10th Workshop on Synthesis And System Integration of Mixed Technologies},
  year = 2001,
}

@article{CTT100457323,
  author = {米田友洋},
  title = {有限幅遅延モデルに基づく非同期式回路検証方式とその効率化},
  journal = {システム/制御/情報},
  year = 2001,
}

@article{CTT100457321,
  author = {Bin Zhou and Tomohiro Yoneda and Holger Schlingloff},
  title = {Conformance and Mirroring for Timed Asynchronous Circuits},
  journal = {Proc. of ASP-DAC'01},
  year = 2001,
}

@article{CTT100457322,
  author = {森広芳文 and 米田友洋},
  title = {シミュレーションを利用した形式的検証システム},
  journal = {電子情報通信学会和文論文誌},
  year = 2001,
}

@article{CTT100457333,
  author = {Tomoya Kitai and Tomohiro Yoneda},
  title = {Partial order reduction in verification of wheel structured parameterized circuits},
  journal = {Proc. of 2001 Pacific Rim International Symposium on Dependable Computing},
  year = 2001,
}

@article{CTT100440081,
  author = {北井智也 and 米田友洋},
  title = {星状抽象ペトリネットの解析に関する研究},
  journal = {電子情報通信学会技術研究報告},
  year = 2000,
}

@article{CTT100440086,
  author = {小黒裕介 and 岡埜 靖 and 米田友洋},
  title = {データパスを含む非同期式回路の検証について},
  journal = {電子情報通信学会技術研究報告},
  year = 2000,
}

@article{CTT100440085,
  author = {Yoshifumi Morihiro and Tomohiro Yoneda},
  title = {Verifying Stacks and Queues Using Symbolic Simulation Techniques},
  journal = {Proc. of 2000 International Workshop on RTL ATPG & DFT},
  year = 2000,
}

@article{CTT100440084,
  author = {米田友洋},
  title = {ペトリネット理論の非同期式回路検証への応用},
  journal = {第13回回路とシステムワークショップ論文集},
  year = 2000,
}

@article{CTT100440083,
  author = {Tomohiro Yoneda},
  title = {VINAS-P: A tool for trace theoretic verification of timed asynchronous circuits},
  journal = {Proc. of Computer Aided Verification, LNCS 1855},
  year = 2000,
}

@article{CTT100440082,
  author = {Mart Saarepera and Tomohiro Yoneda},
  title = {Implementation of Quasi Delay-Insensitive Boolean Function Blocks},
  journal = {Journal of IEICE},
  year = 2000,
}

@article{CTT100440080,
  author = {Yoshifumi Morihiro and Tomohiro Yoneda},
  title = {Formal Verification of Data-Path Circuits based on Symbolic Simulation},
  journal = {Proc. of 9th Asian Test Symposium},
  year = 2000,
}

@article{CTT100433223,
  author = {TOMOHIRO YONEDA},
  title = {Verification of Abstracted Instruction Cache of TITAC2},
  journal = {Proc. of X IFIP International Conference on Very Large Scale Integration},
  year = 1999,
}

@article{CTT100426081,
  author = {Tomohiro Yoneda and Bin Zhou and Bernd--Holger Schlingloff},
  title = {Verification of bounded delay asynchronous circuits with timed traces},
  journal = {Proc. of 7th International Conference on Algebraic Methodology and Software Technology (AMAST'98)},
  year = 1999,
}

@article{CTT100426082,
  author = {Atsushi Yamazaki and Hiroshi Ryu and Tomohiro Yoneda},
  title = {Verification of Scalable-Delay-Insensitive asynchronous circuits},
  journal = {Journal of IEICE, Letter},
  year = 1999,
}

@article{CTT100426083,
  author = {Minoru TOMISAKA and Tomohiro Yoneda},
  title = {Partial Order Reduction in Symbolic State Space Traversal Using ZBDDs},
  journal = {Journal of IEICE, Letter},
  year = 1999,
}

@article{CTT100426084,
  author = {Tomohiro Yoneda and Hiroshi Ryu},
  title = {Timed Trace Theoretic Verification Using Partial Order Reduction},
  journal = {Proc. of Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)},
  year = 1999,
}

@article{CTT100426085,
  author = {Mart Saarepera and Tomohiro Yoneda},
  title = {A Self-Timed Implementation of Boolean Functions},
  journal = {Proc. of Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)},
  year = 1999,
}

@article{CTT100426086,
  author = {増倉 孝一 and 富坂 稔 and 米田 友洋},
  title = {ZBDDに基づく非同期式回路の検証方式},
  journal = {電子情報通信学会和文論文誌},
  year = 1999,
}

@article{CTT100426087,
  author = {戸島弘詩 and 米田 友洋},
  title = {対称性及び抽象化を利用した検証方式の効率化},
  journal = {電子情報通信学会和文論文誌},
  year = 1999,
}

@article{CTT100426088,
  author = {周 斌 and 米田 友洋},
  title = {有限遅延幅モデルにおける非同期式回路の検証について},
  journal = {電子情報通信学会和文論文誌},
  year = 1999,
}

@article{CTT100426089,
  author = {TOMOHIRO YONEDA},
  title = {Verification of Abstracted Instruction Cache of TITAC2},
  journal = {Proc. of X IFIP International Conference on Very Large Scale Integration},
  year = 1999,
}

@article{CTT100433216,
  author = {Tomohiro Yoneda and Bin Zhou and Bernd-Holger Schlingloff},
  title = {Verification of bounded delay asynchronous circuits with timed traces},
  journal = {Proc. of 7th International Conference on Algebraic Methodology and Software Technology (AMAST'98)},
  year = 1999,
}

@article{CTT100433222,
  author = {Tomohiro Yoneda and Hiroshi Ryu},
  title = {Timed Trace Theoretic Verification Using Partial Order Reduction},
  journal = {Proc. of Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)},
  year = 1999,
}

@article{CTT100417907,
  author = {米田友洋},
  title = {非同期式回路の検証におけるlivenessクラスに関する考察},
  journal = {電子情報通信学会和文論文誌},
  year = 1998,
}

@article{CTT100417906,
  author = {TOMOHIRO YONEDA},
  title = {CTL Model Checking of Time Petri Nets Using Geometric Regions},
  journal = {Journal of IEICE},
  year = 1998,
}

@article{CTT100417905,
  author = {TOMOHIRO YONEDA},
  title = {Verification of parameterized asynchronous circuits : A case study ;},
  journal = {International Conference on Application of Concurrency to System Design(CSD'98)},
  year = 1998,
}

@article{CTT100417902,
  author = {米田友洋},
  title = {プロセス代数に基づく非同期式論理回路の設計検証},
  journal = {電子情報通信学会論文誌},
  year = 1997,
}

@article{CTT100417904,
  author = {米田友洋},
  title = {n安全タイムペトリネットの発火規則について},
  journal = {電子情報通信学会研究速報},
  year = 1997,
}

@article{CTT100417903,
  author = {TOMOHIRO YONEDA},
  title = {Efficient Verification of Parallel Real-Time Systems ; Formal Methods in System Design},
  journal = {Kluwer Academic Publishers},
  year = 1997,
}

@article{CTT100417900,
  author = {TOMOHIRO YONEDA},
  title = {BDDs vs. Zero-Suppressed BDDs : for CTL symbolic model checking of Petri nets},
  journal = {Lecture Note in Computer Science 1166},
  year = 1996,
}

@article{CTT100417901,
  author = {米田友洋},
  title = {タイムペトリネットのCTL記号モデル検査},
  journal = {電子情報通信学会論文誌},
  year = 1996,
}

@article{CTT100417899,
  author = {TOMOHIRO YONEDA},
  title = {Using partial orders for trace theoretic verification of asynchronous circuits},
  journal = {Pro.of Second International Symposium on Advanced Research in Asynchronous Circuits and Systems},
  year = 1996,
}

@article{CTT100417898,
  author = {TOMOHIRO YONEDA},
  title = {Discete analysis of time Petri nets},
  journal = {Proc.of the 1995 Pacific Rim International Symposium on Fault Tolerant Systems},
  year = 1995,
}

@article{CTT100417897,
  author = {TOMOHIRO YONEDA},
  title = {Verification of schedulability of real-time systems with extended time Petri nets},
  journal = {Proc.of the Third Workshop on Parallel and Distributed Real-Time Systems},
  year = 1995,
}

@article{CTT100417896,
  author = {TOMOHIRO YONEDA},
  title = {Improving a fault-tolerant clock synchronization algorithm by overcorrection},
  journal = {Computer Systems Science & Engineering},
  year = 1994,
}

@article{CTT100417895,
  author = {TOMOHIRO YONEDA},
  title = {Efficient verification of parallel real-time systems (共著)},
  journal = {Lecture Note in Computer Science},
  year = 1993,
}

@article{CTT100417894,
  author = {TOMOHIRO YONEDA},
  title = {Acceleration of timing verification method based on time Petri nets},
  journal = {Systems and Computers in Japan},
  year = 1991,
}

@article{CTT100417893,
  author = {TOMOHIRO YONEDA},
  title = {A Fast Timing Verification Method Based on the Independence of Units},
  journal = {Proceedings of 19th International Symposium on Fault-Tolerant Computing},
  year = 1989,
}

@article{CTT100417892,
  author = {TOMOHIRO YONEDA},
  title = {The Container Concept for Relaying Packets in Fault-Tolerant Computer Networks},
  journal = {Proceedings of 16th International Symposium on Fault-Tolerant Computing},
  year = 1986,
}

@article{CTT100417891,
  author = {TOMOHIRO YONEDA},
  title = {Implementation of Interrupt Handler for Loosely-Synchronized TMR Systems},
  journal = {Proceedings of 15th International Symposium on Fault-Tolerant Computing},
  year = 1985,
}

@inproceedings{CTT100749816,
  author = {Masashi Imai and Thiem Van Chu and Kenji Kise and Tomohiro Yoneda},
  title = {The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs,},
  booktitle = {},
  year = 2016,
}

@inproceedings{CTT100704077,
  author = {Tomohiro Yoneda and Masashi Imai and Hiroshi Saito and Kenji Kise},
  title = {Dependable real-Time Task Execution Scheme for a Many-Core Platform},
  booktitle = {},
  year = 2015,
}

@inproceedings{CTT100684201,
  author = {宮崎純 and 米田友洋 and 当麻喜弘},
  title = {拡張時間順序機械に基づく自動タイミング検証方式の並列化},
  booktitle = {情報処理学会研究報告システムLSI設計技術},
  year = 1992,
}

@misc{CTT100595034,
  author = {TOMOHIRO YONEDA},
  title = {マイクロコンピュータ複合体の耐故障設計とその応用に関する研究},
  year = 1985,
}



@phdthesis{CTT100595034,
  author = {TOMOHIRO YONEDA},
  title = {マイクロコンピュータ複合体の耐故障設計とその応用に関する研究},
  school = {東京工業大学},
  year = 1985,
}