@article{CTT100796054,
  author = {Bangan Liu and Huy Cu Ngo and Kengo Nakata and Wei Deng and Yuncheng Zhang and Junjun Qiu and Toru Yoshioka and Jun Emmei and Jian Pang and Tn Aravind and Haosheng Zhang and Dongsheng Yang and Hanli Liu and Teruki Someya and Atsushi Shirane and Kenichi Okada},
  title = {A 0.4ps-Jitter -52dBc-Spur Synthesizable Injection-locked PLL with Self-clocked Non-overlap Update and Slope-balanced Sub-sampling BBPD},
  journal = {IEEE Solid-State Circuits Letters (SSC-L)},
  year = 2019,
}

@article{CTT100789869,
  author = {Bangan Liu and Yun Wang and Jian Pang and Haosheng Zhang and Dongsheng Yang and Tn Aravind and Dae-Young Lee and SungTae Choi and Rui Wu and Kenichi Okada and Akira Matsuzawa},
  title = {A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS},
  journal = {IEICE Transactions on Electronics},
  year = 2018,
}

@article{CTT100737555,
  author = {Tn Aravind and Wei Deng and Dongsheng Yang and Rui Wu and Kenichi Okada and Akira Matsuzawa},
  title = {A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI},
  journal = {IEICE Transactions on Electronics},
  year = 2017,
}

@article{CTT100710991,
  author = {Dongsheng Yang and Tomohiro Ueno and Wei Deng and Kengo Nakata and Tn Aravind and Rui Wu and Kenichi Okada and Akira Matsuzawa},
  title = {A 0.0055mm2 480µW Synthesizable PLL using Stochastic TDC in 28nm FDSOI},
  journal = {IEICE Transactions on Electronics},
  year = 2016,
}

@article{CTT100696616,
  author = {Dongsheng Yang and Wei Deng and Tn Aravind and Rui Wu and Bangan Liu and Kenichi Okada and Akira Matsuzawa},
  title = {A Fully Synthesizable Injection-Locked PLL with Feedback Current Output DAC in 28nm FDSOI},
  journal = {IEICE Electronics Express},
  year = 2015,
}

@article{CTT100676904,
  author = {Wei Deng and Dongsheng Yang and Tomohiro Ueno and Teerachot Siriburanon and Satoshi Kondo and Kenichi Okada and Akira Matsuzawa},
  title = {A Fully Synthesizable All-digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-resolution Digital Varactor Using Gated Edge Injection Technique},
  journal = {IEEE Journal of Solid-State Circuits},
  year = 2015,
}

@inproceedings{CTT100816255,
  author = {Bangan Liu and Huy Cu Ngo and Kengo Nakata and Wei Deng and Yuncheng Zhang and Junjun Qiu and Toru Yoshioka and Jun Emmei and Haosheng Zhang and Jian Pang and Tn Aravind and Dongsheng Yang and Hanli Liu and Kenichi Okada and Akira Matsuzawa},
  title = {A 1.2 ps-Jitter Fully-Synthesizable Fully-Calibrated Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique},
  booktitle = {},
  year = 2018,
}

@inproceedings{CTT100737561,
  author = {Dongsheng Yang and Wei Deng and Bangan Liu and Tn Aravind and Teerachot Siriburanon and Kenichi Okada and Akira Matsuzawa},
  title = {An HDL-Synthesized Injection-Locked PLL Using LC-Based DCO for On-chip Clock Generation},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100734469,
  author = {Dongsheng Yang and Wei Deng and Yuki Terashima and Teerachot Siriburanon and Tn Aravind and Toru Yoshioka and Kenichi Okada and Akira Matsuzawa},
  title = {An LC-VCO based Synthesizable Injection-Locked PLL with an FoM of -250.3dB},
  booktitle = {},
  year = 2016,
}

@inproceedings{CTT100702378,
  author = {Dongsheng Yang and Wei Deng and 中田 憲吾 and Teerachot Siriburanon and 岡田 健一 and 松澤 昭},
  title = {A Fully Synthesized Fractional-N IL-PLL Using Only Digital Library},
  booktitle = {},
  year = 2016,
}

@inproceedings{CTT100702367,
  author = {Dongsheng Yang and Wei Deng and Tharayil Narayanan Aravind and Kengo Nakata and Teerachot Siriburanon and Kenichi Okada and Akira Matsuzawa},
  title = {An Automatic Place-and-Routed Two-Stage Fractional-N Injection-locked PLL Using Soft Injection},
  booktitle = {},
  year = 2016,
}

@inproceedings{CTT100691242,
  author = {中田 憲吾 and Wei Deng and Dongsheng Yang and 上野 智大 and THARAYILNAARAVIND and Teerachot Siriburanon and 近藤 智史 and 岡田 健一 and 松澤 昭},
  title = {注入同期を利用した自動合成配置配線可能なAll Digital Synthesizable PLL},
  booktitle = {},
  year = 2015,
}

@inproceedings{CTT100684033,
  author = {.Wei Deng and Dongsheng Yang and Aravind Tharayil Narayanan, and Kengo Nakata and Teerachot Siriburanon and Kenichi Okada and Akira Matsuzawa},
  title = {A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique},
  booktitle = {},
  year = 2015,
}

@inproceedings{CTT100679635,
  author = {Wei Deng and Dongsheng Yang and Tn Aravind and Kengo Nakata and Teerachot Siriburanon and Kenichi Okada and Akira Matsuzawa},
  title = {A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique},
  booktitle = {},
  year = 2015,
}

@inproceedings{CTT100679631,
  author = {Dongsheng Yang and Wei Deng and Tomohiro Ueno and Teerachot Siriburanon and Satoshi Kondo and Kenichi Okada and Akira Matsuzawa},
  title = {An HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC},
  booktitle = {},
  year = 2015,
}

@inproceedings{CTT100676973,
  author = {AravindTharayil Narayanan and Wei Deng and Yang Dongsheng and Wu Rui and Kenichi Okada and Akira Matsuzawa},
  title = {A 0.011 mm2 PVT‐Robust Fully‐Synthesizable CDR with a Data Rate of 10.05 Gb/S Using Injection‐},
  booktitle = {},
  year = 2014,
}

@inproceedings{CTT100673643,
  author = {Wei Deng and Dongsheng Yang and Tomohiro Ueno and Teerachot Siriburanon and Satoshi Kondo and Kenichi Okada and Akira Matsuzawa},
  title = {A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique},
  booktitle = {},
  year = 2014,
}

@inproceedings{CTT100668089,
  author = {Dongsheng Yang and Wei Deng and Teerachot Siriburanon and 岡田 健一 and 松澤 昭},
  title = {A 0.4ps/bit Digitally-controlled Varactor for a Fully Synthesizable DCO},
  booktitle = {},
  year = 2014,
}

@inproceedings{CTT100668090,
  author = {Wei Deng and Dongsheng Yang and Tomohiro Ueno and Teerachot Siriburanon and Kenichi Okada and Akira Matsuzawa},
  title = {Digitally Synthesized PLL with a DAC and Phase-Coupled Oscillator using Standard Cells Only},
  booktitle = {},
  year = 2014,
}

@inproceedings{CTT100668041,
  author = {Wei Deng and Dongsheng Yang and Tomohiro Ueno and Teerachot Siriburanon and Satoshi Kondo and Kenichi Okada and Akira Matsuzawa},
  title = {A 0.0066-mm2 780-µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique},
  booktitle = {},
  year = 2014,
}

@misc{CTT100736704,
  author = {Dongsheng Yang},
  title = {A Study of Synthesizable Phase-Locked Loop for Clock Generation},
  year = 2017,
}

@misc{CTT100760578,
  author = {Dongsheng Yang},
  title = {A STUDY OF SYNTHESIZABLE PHASE-LOCKED LOOP FOR CLOCK GENERATION},
  year = 2017,
}

@misc{CTT100736703,
  author = {Dongsheng Yang},
  title = {A STUDY OF SYNTHESIZABLE PHASE-LOCKED LOOP FOR CLOCK GENERATION},
  year = 2017,
}

@misc{CTT100736705,
  author = {Dongsheng Yang},
  title = {A Study of Synthesizable Phase-Locked Loop for Clock Generation},
  year = 2017,
}



@phdthesis{CTT100736704,
  author = {Dongsheng Yang},
  title = {A Study of Synthesizable Phase-Locked Loop for Clock Generation},
  school = {東京工業大学},
  year = 2017,
}

@phdthesis{CTT100760578,
  author = {Dongsheng Yang},
  title = {A STUDY OF SYNTHESIZABLE PHASE-LOCKED LOOP FOR CLOCK GENERATION},
  school = {東京工業大学},
  year = 2017,
}

@phdthesis{CTT100736703,
  author = {Dongsheng Yang},
  title = {A STUDY OF SYNTHESIZABLE PHASE-LOCKED LOOP FOR CLOCK GENERATION},
  school = {東京工業大学},
  year = 2017,
}

@phdthesis{CTT100736705,
  author = {Dongsheng Yang},
  title = {A Study of Synthesizable Phase-Locked Loop for Clock Generation},
  school = {東京工業大学},
  year = 2017,
}