論文

• Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada. A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 12, pp. 3478-3492, Dec. 2019.
• Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Jian Pang, Tn Aravind, Haosheng Zhang, Dongsheng Yang, Hanli Liu, Teruki Someya, Atsushi Shirane, Kenichi Okada. A 0.4ps-Jitter -52dBc-Spur Synthesizable Injection-locked PLL with Self-clocked Non-overlap Update and Slope-balanced Sub-sampling BBPD, IEEE Solid-State Circuits Letters (SSC-L), Vol. 2, No. 1, pp. 5-8, Jan. 2019.
• Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu, Kenichi Okada. A DPLL-Centric Bluetooth Low-Energy Transceiver with a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS, IEEE Journal of Solid-State Circuits, Vol. 53, No. 12, pp. 3672-3687, Dec. 2018.
• Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada. A Sub-mW Fractional-N ADPLL with FOM of -246dB for IoT Applications, IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, pp. 3540-3552, Dec. 2018.
• Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa. A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS, IEICE Transactions on Electronics, Vol. E101-C, No. 4, pp. 187-196, Apr. 2018.
• Tn Aravind, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa. A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI, IEICE Transactions on Electronics, Vol. E100-C, No. 3, pp. 259-267, Mar. 2017.
• Tn Aravind, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Fractional-N Sub-Sampling PLL Using a Pipelined Phase-Interpolator with an FoM of -250dB, IEEE Journal of Solid-State Circuits, IEEE, Vol. 51, No. 7, pp. 1630-1640, July 2016.
• Kenichi Okada, Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng. A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture, IEEE Journal of Solid-State Circuits, Vol. 51, No. 6, pp. 1385-1397, June 2016.
• Dongsheng Yang, Tomohiro Ueno, Wei Deng, Kengo Nakata, Tn Aravind, Rui Wu, Kenichi Okada, Akira Matsuzawa. A 0.0055mm2 480µW Synthesizable PLL using Stochastic TDC in 28nm FDSOI, IEICE Transactions on Electronics, IEICE, Vol. E99-C, No. 6, pp. 632-640, June 2016.
• Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Low-Power Low-Noise mm-Wave Sub-Sampling PLL using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad, IEEE Journal of Solid-State Circuits, IEEE, Vol. 51, No. 5, pp. 1246-1260, May 2016.
• Dongsheng Yang, Wei Deng, Tn Aravind, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa. A Fully Synthesizable Injection-Locked PLL with Feedback Current Output DAC in 28nm FDSOI, IEICE Electronics Express, IEICE, Vol. 12, No. 15, pp. 1-11, Aug. 2015.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit, IEICE Transactions on Electronics, IEICE, Vol. E98-C, No. 6, pp. 471-479, June 2015.
• Rui Wu, Wei Deng, Shinji Sato, Takuichi Hirano, Ning Li, Takeshi Inoue, Hitoshi Sakane, Kenichi Okada, Akira Matsuzawa. A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections, IEICE Transactions on Electronics, IEICE, Vol. 98-C, No. 4, pp. 304-314, Apr. 2015.
• Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa. A Fully Synthesizable All-digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-resolution Digital Varactor Using Gated Edge Injection Technique, IEEE Journal of Solid-State Circuits, Vol. 50, No. 1, pp. 68-80, Jan. 2015.
• Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer using Self-synchronized Gating Injection Technique for Software-defined Radios, IEEE Journal of Solid-State Circuits, Vol. 49, No. 9, pp. 1984-1994, Sept. 2014.
• Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration, IEEE Journal of Solid-State Circuits, Vol. 49, No. 1, pp. 50-60, Jan. 2014.
• Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers, IEEE Journal of Solid-State Circuits, Vol. 48, No. 7, pp. 1710-1720, July 2013.
• Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 20GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60GHz Frequency Synthesizer, IEICE Transactions on Electronics, Vol. E96-C, No. 6, pp. 804-812, June 2013.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. Class-C VCO with Amplitude Feedback Loop for Robust Start-up and Enhanced Oscillation Swing,, IEEE Journal of Solid-State Circuits, Vol. 48, No. 2, pp. 429-440, Feb. 2013.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition, IEICE Transactions on Electronics, Vol. E95-C, No. 7, pp. 1285-1296, July 2012.

著書

• Teerachot Siriburanon, Hanli Liu, Kenichi Okada, Akira Matsuzawa, Wei Deng, Satoshi Kondo, Makihiko Katsuragi, Kento Kimura. IoT and Low-Power Wireless: Circuits, Architectures, and Techniques, CRC Press, July 2018.
• Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. Low Phase Noise Quadrature Frequency Synthesizer for 60 GHz Radios, CRC Press, pp. 491-514, Nov. 2014.

国際会議発表 (査読有り)

• Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada. An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator Based Frequency Synthesizer and Digital Background EVM Calibration, IEEE Custom Integrated Circuits Conference (CICC), Apr. 2019.
• Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada. A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS, IEEE International Solid-State Circuits Conference (ISSCC), pp. 256-257, Feb. 2019.
• Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Tohru Kaneko, Rui Wu, Wei Deng, Kenichi Okada. A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver, IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 310-313, Sept. 2018.
• Jian Pang, Rui Wu, Yun Wang, Masato Dome, Hisashi Kato, Hongye Huang, Tn Aravind, Hanli Liu, Wei Deng, Bangan Liu, Takeshi Nakamura, Takuya Fujimura, Masaru Kawabuchi, Ryo Kubozoe, Tsuyoshi Miura, Daiki Matsumoto, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Kenichi Okada. A 28GHz CMOS Phased-Array Transceiver Using Gain-Invariant LO Phase Shifter with 0.1 Degree Beam-Steering Resolution for 5G New Radio, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 56-59, June 2018.
• Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Tn Aravind, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa. A 1.2 ps-Jitter Fully-Synthesizable Fully-Calibrated Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique, IEEE Custom Integrated Circuits Conference (CICC), Apr. 2018.
• Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa. A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FoM of -246dB for IoT Applications in 65nm CMOS, IEEE International Solid-State Circuits Conference, Feb. 2018.
• Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, Akira Matsuzawa. An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS, IEEE International Solid-State Circuits Conference, Feb. 2018.
• Dongsheng Yang, Wei Deng, Bangan Liu, Tn Aravind, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. An HDL-Synthesized Injection-Locked PLL Using LC-Based DCO for On-chip Clock Generation, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC),, Jan. 2017.
• Dongsheng Yang, Wei Deng, Yuki Terashima, Teerachot Siriburanon, Tn Aravind, Toru Yoshioka, Kenichi Okada, Akira Matsuzawa. An LC-VCO based Synthesizable Injection-Locked PLL with an FoM of -250.3dB, IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2016.
• Dongsheng Yang, Wei Deng, Tharayil Narayanan Aravind, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. An Automatic Place-and-Routed Two-Stage Fractional-N Injection-locked PLL Using Soft Injection, IEEE ACM Asia South Pacific Design Automation Conference, Jan. 2016.
• Teerachot Siriburanon, Liu Hanli, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa. A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Cellular, IEEE European Solid-State Circuits Conference, Sept. 2015.
• Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Yuki Terashima, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with an FoM of -246dBc/Hz, IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2015.
• Wei Deng, Dongsheng Yang, Tn Aravind, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique, IEEE International Solid-State Circuits Conference (ISSCC),, Feb. 2015.
• Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture, IEEE International Solid-State Circuits Conference (ISSCC),, Feb. 2015.
• Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 58.3-to-65.4GHz 34.2mW Sub-Harmonically Injection-Locked PLL with a Sub-Sampling Phase Detection,, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2015.
• Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa. An HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2015.
• AravindTharayil Narayanan, Wei Deng, Yang Dongsheng, Wu Rui, Kenichi Okada, Akira Matsuzawa. A 0.011 mm2 PVT‐Robust Fully‐Synthesizable CDR with a Data Rate of 10.05 Gb/S Using Injection‐, IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2014.
• Rui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 0.015-mm2 60-GHz Reconfigurable Wake-Up Receiver by Reusing Multi-Stage LNAs, IEEE Asian Solid-State Circuits Conference (A-SSCC),, Nov. 2014.
• Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Tail-Feedback VCO with Self-Adjusting Current Modulation Scheme, IEEE MTT-S European Microwave Conference (EuMC), Oct. 2014.
• Wu Rui, Wei Deng, Shinji Sato, Takuichi Hirano, Ning Li, Takeshi Inoue, Hitoshi Sakane, Kenichi Okada, Akira Matsuzawa. A 60-GHz Efficiency-Enhanced On-Chip Dipole Antenna Using Helium-3 Ion Implantation Process, IEEE MTT-S European Microwave Conference (EuMC), Oct. 2014.
• Aravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Pulse-Driven LC-VCO with a Figure-of-Merit of -192dBc/Hz,, IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2014.
• Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 60-GHz Sub-Sampling Frequency Synthesizer Using Sub-Harmonic Injection-Locked Quadrature Oscillators, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2014.
• Rui Wu, Wei Deng, Shinji Sato, Takuichi Hirano, Ning Li, Takeshi Inoue, Hitoshi Sakane, Kenichi Okada, Akira Matsuzawa. A 17-mW 5-Gb/s 60-GHz CMOS Transmitter with Efficiency-Enhanced On-Chip Antenna, IEEE Radio Frequency Integrated Circuits Symposium (RFIC),, June 2014.
• Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa. A 0.0066-mm2 780-µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique, IEEE International Solid-State Circuits Conference (ISSCC), pp. 266-267, Feb. 2014.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A Dual-loop Injection-locked PLL with All-digital Background Calibration System for On-chip Clock Generation, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), pp. 21-22, Jan. 2014.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Swing-Enhanced Current-Reuse Class-C VCO with Dynamic Bias Control Circuits, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), pp. 25-26, Jan. 2014.
• .Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A Dual-Step-Mixing ILFD using a Direct Injection Technique for High-Order Division Ratios in 60GHz Applications, IEICE Thailand-Japan MicroWave (TJMW), Dec. 2013.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Constant-Current-Controlled Class-C VCO using a Self-Adjusting Replica Biasing Scheme, IEEE MTT-S European Microwave Conference, Oct. 2013.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A 13.2% Locking-Range Divide-by-6, 3.1mW, ILFD Using Even-Harmonic-Enhanced Direct Injection Technique for Millimeter-Wave PLLs, IEEE European Solid-State Circuits Conference, Sept. 2013.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Current-Reuse Class-C LC-VCO with an Adaptive Bias Scheme,, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2013.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A 60GHz PVT-Tolerant Injection-locked Frequency Synthesizer with a Background Calibration Technique, IEEE EDS WIMNACT-37 Future Trend of Nanodevices and Photonics,, Feb. 2013.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A 0.022mm2 970µW Injection-Locked PLL with -243dB FOM using Synthesizable All-Digital PVT Calibration Circuits, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2013.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A Sub-harmonic Injection-locked Frequency Synthesizer with Frequency Calibration Scheme for Use in 60GHz TDD Transceivers, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2013.
• Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A Fractional-N Harmonic Injection-locked Frequency Synthesizer with 10MHz-6.6GHz Quadrature Outputs for Software-Defined Radios, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC),, Jan. 2013.
• Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 20 GHz Push-Push Voltage-Controlled Oscillator for a 60 GHz Frequency Synthesizer, IEEE Asia-Pacific Microwave Conference (APMC), Dec. 2012.
• Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A 0.38mm2, 10MHz-6.6GHz Quadrature Frequency Synthesizer Using Fractional-N Injection-Locked Technique, IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2012.
• Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. "A 58.1-to-65.0GHz Frequency Synthesizer with Background Calibration for Millimeter-wave TDD Transceivers,", IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2012.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. A PVT-robust Feedback Class-C VCO Using an Oscillation Swing Enhancement Technique, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC),, pp. 563-564, Jan. 2012.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. "A Feedback Class-C VCO with Robust Startup Condition over PVT Variations and Enhanced Oscillation Swing,", IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2011.
• "Wei Deng, Kenichi Okada, Akira Matsuzawa. A 25MHz-6.44GHz LC-VCO Using a 5-port Inductor for Multi-band Frequency Generation, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2011.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. An Ultra-Low-Voltage LC-VCO with a Frequency Extension Circuit for Future 0.5-V Clock Generation, IEEE ACM Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2011.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. "A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond jitter clock generation", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 93-96, Nov. 2010.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. Phase Noise Scaling of LC-VCO for Ultra Low Supply Voltage, URSI Asia-Pacific Radio Science Conference(AP-RASC), Sept. 2010.

国内会議発表 (査読有り)

• Tn Aravind, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Tail-Current Modulated VCO with Adaptive-Bias Scheme, EEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2015.
• 竹内 康揚, 原 翔一, ウェイ デン, 岡田 健一, 松澤 昭. ソフトウェア無線へ向けたCMOSマルチバンド電圧制御発振器の研究, 電子情報通信学会 ソフトウェア無線研究会, Vol. SR2011-21(2011-7), July 2011.

国際会議発表 (査読なし・不明)

• Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Tail-Current Modulated VCO with Adaptive Start-up Scheme, Vietnam Japan MicroWave, Nov. 2014.
• Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Tail-Current Modulated VCO with Adaptive Startup Scheme, Thailand-Japan Microwave (TJMW2014), Nov. 2014.
• Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 60-GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD,(invited), IEEE Asia-Pacific Microwave Conference (APMC), Nov. 2014.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. Phase noise scaling of LC voltage-controlled oscillator for future 0.5-V sub-picosecond-jitter clock generation, International Workshop on Millimeter Wave Wireless Technology and Applications, pp. 128-129, Dec. 2010.

国内会議発表 (査読なし・不明)

• Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang, Rui Wu, 染谷 晃基, 白根 篤史, 岡田 健一. A 21.7% System Power Efficiency Fully-Synthesizable Transmitter for sub-GHz IoT Applications, 電子情報通信学会 ソサイエティ大会, Sept. 2019.
• Dingxin Xu, Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, 染谷 晃基, 白根 篤史, 岡田 健一. A 265-µW Fractional-N Digital PLL with Switching Subsampling/Sampling Feedback, 電子情報通信学会 LSIとシステムのワークショップ, May 2019.
• Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, 金子 徹, Rui Wu, Wei Deng, 染谷 晃基, 白根 篤史, 岡田 健一. A T/R Switch Embedded BLE Transceiver with 2.6mW Harmonic-Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver」,, 電子情報通信学会 LSIとシステムのワークショップ, May 2019.
• Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Tohru Kaneko, Rui Wu, Wei Deng, Teruki Someya, Atsushi Shirane, Kenichi Okada. A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver, 電子情報通信学会 集積回路研究会, Vol. ICD2018-115, No. 507, pp. 81-85, Mar. 2019.
• Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Pang Jian, Yun Wang, Rui Wu, 染谷 晃基, Atsushi Shirane, Kenichi Okada. A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS, IEEE SSCS Japan Chapter ISSCC報告会, Mar. 2019.
• Bangan Liu, Huy Cu Ngo, Wei Deng, Yuncheng Zhang, Junjun Qiu, Kengo Nakata, Teruki Someya, Atsushi Shirane, Kenichi Okada. A 1.2 ps-Jitter Fully-Synthesizable DTC-based Fractional-N Injection-Locked PLL using True Arbitrary Nonlinearity Calibration, 電子情報通信学会 ソサイエティ大会, Sept. 2018.
• Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, 金子 徹, Wei Deng, Rui Wu, 白根 篤史, 岡田 健一. An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS, 電子情報通信学会 LSIとシステムのワークショップ, May 2018.
• Hongye Huang, Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, 白根 篤史, 岡田 健一. An Ultra-Low-Power Fractional-N All-Digital PLL Using 10-bit Isolated Constant-Slope Digital-to-Time Converter, 電子情報通信学会 LSIとシステムのワークショップ, May 2018.
• Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 28GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G New Radio, 電子情報通信学会 集積回路研究会, Vol. ICD2017-89, pp. 147-150, Dec. 2017.
• Dongsheng Yang, Wei Deng, 中田 憲吾, Teerachot Siriburanon, 岡田 健一, 松澤 昭. A Fully Synthesized Fractional-N IL-PLL Using Only Digital Library, 電子情報通信学会 総合大会, C-12-9, Mar. 2016.
• 中田 憲吾, Wei Deng, Dongsheng Yang, 上野 智大, THARAYILNAARAVIND, Teerachot Siriburanon, 近藤 智史, 岡田 健一, 松澤 昭. 注入同期を利用した自動合成配置配線可能なAll Digital Synthesizable PLL, 電子情報通信学会 LSIとシステムのワークショップ, May 2015.
• .Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan,, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique, IEEE SSCS Kansai Chapter ISSCC報告会, Mar. 2015.
• Rui Wu, Qinghong Bu, Wei Deng, 岡田 健一, 松澤 昭. An Ultra-Compact 60-GHz Wake-Up Receiver by Reconfiguring Multi-Stage LNAs, 電子情報通信学会 アナログRF研究会, Vol. Vol.RF2014-3, p. 3, Mar. 2015.
• Teerachot Siriburanon, 近藤 智史, 木村 健将, 上野 智大, 川嶋 理史, 金子 徹, Wei Deng, 宮原 正也, 岡田 健一, 松澤 昭. A Digital Sub-sampling ADC-PLL with -112dBc/Hz In-band Phase Noise and 380fsrms Jitter, 電子情報通信学会 アナログRF研究会, Mar. 2015.
• Tn Aravind, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Pulse-Driven VCO with Enhanced Efficiency, 電子情報通信学会 アナログRF研究会, Vol. RF2014-2, p. 2, Dec. 2014.
• Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa. A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique, IEEE SSCS Japan Chapter ISSCC報告会, May 2014.
• Dongsheng Yang, Wei Deng, Teerachot Siriburanon, 岡田 健一, 松澤 昭. A 0.4ps/bit Digitally-controlled Varactor for a Fully Synthesizable DCO, 電子情報通信学会 総合大会, C-12-36, Mar. 2014.
• Teerachot Siriburanon, Wei Deng, Ahmed Magdi Hassan Musa, Kenichi Okada, Akira Matsuzawa. A Dual-Step-Mixing ILFD using a Direct Injection Technique for High-Order Division Ratios in 60GHz Applications, 電子情報通信学会 総合大会, CI-1-3, Mar. 2014.
• Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. Digitally Synthesized PLL with a DAC and Phase-Coupled Oscillator using Standard Cells Only, 電子情報通信学会 総合大会, C-12-30, Mar. 2014.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, 岡田 健一, 松澤 昭. A Divide-by-4 and Divide-by-6 Injection-locked Frequency Divider using Even-Harmonic Direct Injection Method for V-band Applications, 電子情報通信学会 アナログRF研究会, Vol. RF2013-2, p. 1, Nov. 2013.
• Teerachot Siriburanon, Wei Deng, 岡田 健一, 松澤 昭. A Current-Reuse Class-C VCO using Dynamic Start-up Circuits, 電子情報通信学会 ソサイエティ大会, 電子情報通信学会ソサイエティ大会講演論文集, C-12-32, Sept. 2013.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, 宮原 正也, 岡田 健一, 松澤 昭. A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System, 電子情報通信学会 総合大会, C-12-58, Mar. 2013.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, 宮原 正也, 岡田 健一, 松澤 昭. A PVT-tolerant Dual-loop Injection-locked PLL for Clock Generation, 電子情報通信学会 シリコンアナログRF研究会, Vol. RF2012-4, p. 4, Mar. 2013.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, 宮原 正也, 岡田 健一, 松澤 昭. A 0.022mm2 970µW Injection-Locked PLL with -243dB FOM using Synthesizable All-Digital PVT Calibration Circuits, IEEE SSCS 関西 Chapter ISSCC報告会, Mar. 2013.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A 60GHz PVT-tolerant Injection-locked Frequency Synthesizer with a Background Frequency Calibration Technique, 電子情報通信学会 シリコンアナログRF研究会, Vol. RF2012-3, p. 7, Dec. 2012.
• Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A 10MHz-6.6GHz Quadrature-Output Frequency Synthesizer for Multi-band Transceivers, 電子情報通信学会 シリコンアナログRF研究会, Vol. RF2012-3, p. 6, Dec. 2012.
• Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 20GHz Push-Push Voltage-Controlled Oscillator for a MM-Wave Frequency Synthesizer, 電子情報通信学会 ソサイエティ大会, C-12-15, Sept. 2012.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. A Startup Ensured Class-C VCO with Enhanced Oscillation Swing, 電子情報通信学会 総合大会, C-12-66, Mar. 2012.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Wide Frequency Range 60GHz Static Frequency Divider Using Shunt-Series Peaking, 電子情報通信学会 ソサイエティ大会, C-12-33, Sept. 2011.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. "A 25MHz-6.44GHz LC-VCO Using a 5-port Inductor for Multi-band Frequency Generation", 電子情報通信学会 シリコンアナログRF研究会, Vol. RF-2011-2, p. 2, Aug. 2011.
• Wei Deng, Kenichi Okada, Akira Matsuzawa. Design of 0.5-V LC-VCO for Low-voltage and Low-jitter Clock Generator, 電子情報通信学会 総合大会, C-12, Mar. 2011.

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